US 11,537,397 B2 · Compiler-assisted inter-SIMD-group register sharing

Abstract

Systems, apparatuses, and methods for efficiently sharing registers among threads are disclosed. A system includes at least a processor, control logic, and a register file with a plurality of registers. The processor assigns a base set of registers to each thread of a plurality of threads executing on the processor. When a given thread needs more than the base set of registers to execute a given phase of program code, the given thread executes an acquire instruction to acquire exclusive access to an extended set of registers from a shared resource pool. When the given thread no longer needs additional registers, the given thread executes a release instruction to release the extended set of registers back into the shared register pool for other threads to use. In one implementation, the compiler inserts acquire and release instructions into the program code based on a register liveness analysis performed during compilation.

Claims20

Dependent claims

A processor comprising:

a cache;
one or more execution units comprising circuitry configured to execute instructions fetched from the cache;
a register file comprising a plurality of registers;
and
control logic coupled to the one or more execution units and the plurality of registers;
wherein the control logic comprises circuitry configured to:
allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit of the one or more execution units;
and
in response to detecting that the first thread requires use of an additional number of registers, allocate a second set of registers from the register file for use by the first thread, wherein an index of the second set of registers is at a location indexed by an identifier (ID) of the first thread;
wherein:
the second set of registers are allocated from a pool of registers shared by a plurality of threads;
and
registers of the pool of registers are allocated for use when any of the plurality of threads need an additional number of registers.

10 more elements

A method comprising:

executing instructions fetched from a cache by one or more execution units of a processor;
allocating, by circuitry of control logic of the processor, a first set of registers of a register file comprising a plurality of registers for exclusive use by a first thread executing on the processor;
and
in response to detecting that the first thread requires use of an additional number of registers, allocating a second set of registers from the register file for use by the first thread, wherein an index of the second set of registers is at a location indexed by an identifier (ID) of the first thread;
wherein:
the second set of registers are allocated from a pool of registers from the register file shared by a plurality of threads;
and
registers of the pool of registers are allocated for use when any of the plurality of threads needs an additional number of registers.

5 more elements

A system comprising:

a processor coupled to a memory;
wherein the processor is configured to:
execute instructions fetched from a cache;
allocate a first set of registers of a register file comprising a plurality of registers for exclusive use by a first thread;
and
in response to detecting that the first thread requires use of an additional number of registers, allocate a second set of registers from the register file for use by the first thread, wherein an index of the second set of registers is at a location indexed by an identifier (ID) of the first thread;
wherein:
the second set of registers are allocated from a pool of registers from the register file shared by a plurality of threads;
and
registers of the pool of registers are allocated for use when any of the plurality of threads needs an additional number of registers.

7 more elements

Dependencies are inferred from the claim text.

Compiler-assisted inter-SIMD-group register sharing

Life of this patent

Compiler-assisted inter-SIMD-group register sharing

Life of this patent

Abstract

Claims20