Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method

An apparatus comprising:

• a voltage regulator to generate a supply voltage;
• a clock source to generate a clock;
• a computational block coupled to the voltage regulator and the clock source, wherein the computational block is to receive a supply voltage and a clock;
• and
• control circuitry to reduce the supply voltage and a frequency of the clock within a period less than 100 nanoseconds of a signal that indicates a longer than normal latency operation, wherein the control circuitry is further to:
• provide an early indication that data is available from a memory;
• instruct the clock source to increase frequency of the clock back to pre-reduction level;
• and
• instruct the voltage regulator to increase voltage level of the supply voltage to a pre-existing supply voltage level, wherein the voltage level of the supply voltage is increased prior to increase of frequency of the clock.

An apparatus comprising:

• a processor core to execute one or more instructions;
• a voltage regulator coupled to the processor core, wherein the voltage regulator is to provide an adjustable power supply voltage to the processor core;
• a clock generator coupled to the processor core, wherein the clock generator is to provide an adjustable clock to the processor core;
• a cache coupled to the processor core;
• and
• control circuitry to determine whether data to execute the one or more instructions is available from the cache, and to indicate a cache miss if data is not available from the cache, wherein the circuitry is to:
• instruct the clock generator to reduce frequency of the clock;
• and
• instruct the voltage regulator to reduce voltage level of the adjustable power supply, wherein the frequency of the clock is reduced prior to voltage level of the adjustable power supply is reduced;
• and
• charge transfer circuitry coupled to the voltage regulator, wherein the charge transfer circuitry is to temporarily transfer charge from an output capacitor, coupled to a power supply rail that provides adjustable power supply voltage to the processor core, to an inductor or another capacitor within a period of the indication of the cache miss.