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US 11,537,327 B2Granted
Adaptive watchdog in a memory device
AssigneeMicron Technology, Inc.
InventorsNadav Grosz, David Aaron Palmer
Life of this patent
Estimating the term…
Abstract
Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.
Claims20
A memory device, comprising:
- a memory array;
- and
- a memory controller configured to control operations on the memory array, the memory controller comprising a timer triggered in association with an operation on the memory array, wherein the memory controller is configured to perform operations comprising:
- receive a command for a first memory operation of a first type from a host at a first time;
- receive at a second time following the first time, a reset signal from the host;
- measure a time interval between the first time and the second time;
- establish, based on the measured time interval, a first delay interval for the timer of the memory device for the first type of memory operation to perform a reset operation independent of a reset signal from the host;
- receive a command for a second memory operation of the first type from the host at a third time;
- and
- in response to receiving the command for the second memory operation, initiating the timer to count the first delay interval before resetting the memory device independent of receiving a further reset signal from the host.
7 more elements
A memory device, comprising:
- a memory array;
- and
- a memory controller configured to control operations on the memory array, the memory controller comprising a timer module comprising one or more timers, wherein the memory controller is configured to perform operations comprising:
- using the timer module to monitor a latency of performing write operations on one or more memory devices of the memory array;
- using the timer module to monitor a latency of performing read operations on one or more memory devices of the memory array;
- in response to the monitored latency of performing write operations, establishing at least one timer interval for performing write operations before resetting of the memory device independent of a reset signal from the host;
- in response to the monitored latency of performing read operations,
- establishing at least one timer interval for performing read operations before resetting of the memory device independent of a reset signal from the host.
5 more elements
Dependencies are inferred from the claim text.