Content addressable memory with sub-field minimum and maximum clamping
AssigneeAdvanced Micro Devices, Inc.
InventorsAlexander Fuad Ashkar, James R. Klobcar, Harry J. Wise
Life of this patent
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Abstract
A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.
Claims18
A method comprising:
- receiving, at a processing system comprising a plurality of processing pipelines, first data associated with a first address to be written to a first register of the processing system;
- comparing, at a content addressable memory (CAM) of the processing system, the first address to an address field of each entry of the CAM;
- in response to determining that the first address matches the address field of an entry of the CAM, selectively modifying a value of the first data on a per-pipeline basis based on a function select associated with the entry of the CAM;
- and
- writing the modified value to the first register;
- wherein selectively modifying the value of the first data comprises selectively modifying the value of the first data for a first pipeline based on an indication that the first pipeline is enabled, and selectively modifying the value of the first data for a second pipeline based on an indication that the second pipeline is enabled.
A method, comprising:
- receiving, at a content addressable memory (CAM) of a processing system comprising a plurality of processing pipelines, first data to be written to a register of the processing system;
- in response to the first data matching an entry of the CAM, applying a data mask stored at the entry, the data mask defining one or more subfields of the first data, wherein each subfield comprises subfield data comprising one or more bits;
- and
- performing a first operation on a first subfield of the first data on a per-pipeline basis based on a first function select stored at the matching entry of the CAM, the first operation comprising selectively modifying the value of the first data for a first pipeline based on an indication that the first pipeline is enabled, and selectively modifying the value of the first data for a second pipeline based on an indication that the second pipeline is enabled.
A processing system comprising a plurality of processing pipelines, comprising:
- a register;
- an interface configured to receive first data associated with a first address to be written to the register;
- and
- a content addressable memory (CAM) configured to:
- compare the first address to an address field of each entry of the CAM;
- in response to determining that the first address matches the address field of an entry of the CAM, selectively modify a value of the first data on a per-pipeline basis based on a function select associated with the entry of the CAM, wherein to selectively modify the value of the first data includes to selectively modify the value of the first data for a first pipeline based on an indication that the first pipeline is enabled, and to selectively modify the value of the first data for a second pipeline based on an indication that the second pipeline is enabled;
- and
- write the modified value to the register.
Dependencies are inferred from the claim text.