Memory system and operating method thereof

An operating method of a memory system including a memory device having a plurality of memory dies;

• and a controller having a host interface, a memory interface, and a processor, the memory interface having a command queue, a fail managing buffer, and a queue manager, and the processor having a program manager and a descriptor generator, the operating method comprising:
• enqueuing, by the command queue, a program descriptor and a first read descriptor in the command queue;
• controlling, by the program manager, the memory device to perform an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address included in a second read descriptor which is enqueued in the command queue after a program operation performed on a first physical address fails and the error handling operation has passed;
• temporarily storing, by the fail managing buffer, the first physical address for the failed program operation in the fail managing buffer;
• preventing failed data at the first physical address for the failed program operation from being read by deleting, by the queue manager, the first read descriptor from the command queue and outputting an exception signal, after a physical address included in the first read descriptor is stored in the fail managing buffer;
• and
• generating, by the descriptor manager, the second read descriptor including the second physical address in response to the exception signal and enqueuing the second read descriptor in the command queue.

A memory controller comprising:

• a processor configured to control a program operation and a read operation of the memory device;
• a memory interface configured to interface the processor and a memory device having a plurality of dies;
• and
• a host interface configured to interface the processor and a host device;
• wherein the memory interface comprises:
• a command queue configured to queueing a program descriptor and a first read descriptor therein, and sequentially provide the queued descriptors to the memory device;
• a fail managing buffer configured to temporarily store a first physical address for a failed program operation;
• and
• a queue manager configured to prevent failed data at the first physical address for the failed program operation from being read by deleting the first read descriptor from the command queue and outputting an exception signal, after a physical address in the first read descriptor is stored in the fail managing buffer,
• wherein the processor comprises:
• a program manager configured to controlling the memory device to perform an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address included in a second read descriptor which is enqueued in the command queue after a program operation performed on the first physical address fails and the error handling operation passes;
• and
• a descriptor generator configured to generate the second read descriptor including the second physical address in response to the exception signal and enqueue the second read descriptor in the command queue.