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US 11,537,306 B2Granted
Cold data detector in memory system
AssigneeMicron Technology, Inc.
InventorsYuan He, Daigo Toyama
Life of this patent
Estimating the term…
Abstract
A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.
Claims20
An apparatus comprising:
- a memory cell array comprising a plurality of banks, wherein a bank of the plurality of banks includes a respective plurality of segments each associated with a respective segment address;
- and
- a cold data detector circuit corresponding to the bank of the plurality of banks and comprising a register having a plurality of slots configured to store received segment addresses, wherein, in response to detection that each of the respective plurality of segments of the bank has had at least one access operation, the cold data detector circuit is configured to provide a longest stored segment address from the register to an output as a cold address, wherein each bank of the plurality of banks corresponds to a respective cold data detector circuit.
An apparatus comprising:
- a memory cell array comprising a plurality of banks, wherein a bank of the plurality of banks includes a respective plurality of segments each associated with a respective segment address;
- and
- a cold data detector circuit corresponding to the bank of the plurality of banks and comprising a register having a plurality of slots configured to store received segment addresses, wherein, in response to detection that each of the respective plurality of segments of the bank has had at least one access operation, the cold data detector circuit is configured to provide a longest stored segment address from the register to an output as a cold address, wherein the memory cell array further includes a second cold data detector circuit corresponding to a second bank of the plurality of banks, wherein the second cold data detector circuit includes a second register with a second plurality of slots configured to store received segment addresses associated with a respective plurality of segments of the second bank, wherein, in response to detection that each of the respective plurality of segments of the second bank has had at least one access operation, the second cold data detector circuit is configured to provide a longest stored segment address from the second register to an output as a second cold address.
An apparatus comprising:
- a memory cell array comprising a plurality of banks, wherein a bank of the plurality of banks includes a respective plurality of segments each associated with a respective segment address;
- a cold data detector circuit corresponding to the bank of the plurality of banks and comprising a register having a plurality of slots configured to store received segment addresses, wherein, in response to detection that each of the respective plurality of segments of the bank has had at least one access operation, the cold data detector circuit is configured to provide a longest stored segment address from the register to an output as a cold address;
- and
- a plurality of cold data detector circuits, including the cold data detector circuit, each corresponding to a respective bank of the plurality of banks, wherein, in response to detection that each of the respective plurality of segments of the respective bank has had at least one access operation, each of the plurality of cold data detector circuits is configured to provide a respective longest stored segment address from the respective register as a respective cold address;
- and
- a cold data readout circuit having a shift register having a plurality of slots each configured to store the respective cold address from a particular one of the plurality of cold data detector circuits, wherein the cold data readout circuit is configured to initiate the transfer of cold data from the memory cell array to another memory in response to receipt of a bank full signal from each of the plurality of cold data detectors.
3 more elements
An apparatus comprising:
- a first memory having a first access latency;
- a second memory having a second access latency that is less than the first access latency, wherein the second memory comprises a memory cell array comprising a plurality of banks, wherein each of the plurality of banks includes a respective plurality of segments each associated with a respective segment address, the second memory further comprising a plurality of cold data detector circuits each corresponding to a respective one of the plurality of banks and each comprising a respective register, wherein each of the respective registers is configured to store segment addresses, wherein, in response to detection that each segment of a particular bank has been targeted for at least one access operation, the respective cold data detector of the plurality of cold data detectors is configured to provide a respective longest-stored segment address from the respective register to a cold data readout circuit, wherein the cold data readout circuit is provide an indication to transfer cold data from the first memory to the second memory in response to receipt of the respective longest-stored segment address from each of the plurality of cold data detectors.
A method comprising:
- storing segment addresses at a register of a cold data detector circuit during access operations associated with a bank of a memory cell array having a plurality of segments, wherein the segment addresses are each associated with a respective segment of the plurality of segments;
- in response to detection that each of the plurality of segments of the bank has been accessed, transfer a longest stored segment address to a cold data readout circuit as a cold address;
- and
- in response to receipt of a corresponding longest stored segment address from each of a plurality of registers corresponding to a plurality of banks of the memory cell array, initiating the transfer of cold data from the memory cell array to another memory.
1 more element
Dependencies are inferred from the claim text.