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US 11,537,017 B2Granted
Array substrate and display panel
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorYani Chen
Life of this patent
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Abstract
An array substrate and a display panel are provided. The array substrate includes a plurality of sub-pixels, and each sub-pixel includes four thin film transistors. The array substrate further includes a gate line, a data line, and a divided voltage line. In the present invention, a channel aspect ratio of second thin film transistor is greater than a channel aspect ratio of the first thin film transistor and a channel aspect ratio of third thin film transistor, and a drain of a fourth thin film transistor is electrically connected to the divided voltage line, such that the display panel has a wider viewing angle.
Claims19
An array substrate, comprising:
- a plurality of sub-pixels disposed on the substrate and arranged in an array, wherein each sub-pixel comprises a main area, a first sub-area, and a second sub-area;
- a plurality of gate lines, wherein each gate line is disposed in the sub-pixel in each row, and between the main area and the second sub-area;
- a plurality of data lines and a plurality of divided voltage lines, wherein each data line and each divided voltage line are disposed in the sub-pixel in each column, the two adjacent data lines define a pixel boundary, and the divided voltage line is disposed between two adjacent data lines;
- and
- a pixel electrode, wherein the pixel electrode comprises a main pixel electrode disposed in the main area, a first sub-pixel electrode disposed in the first sub-area, and a second sub-pixel electrode disposed in the second sub-area;
- wherein the sub-pixel further comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the first thin film transistor is electrically connected to the first sub-pixel electrode, the second thin film transistor is electrically connected to the main pixel electrode, the third thin film transistor is electrically connected to the second sub-pixel electrode, and the fourth thin film transistor is electrically connected to the divided voltage line;
- and
- wherein a channel aspect ratio of the second thin film transistor is greater than a channel aspect ratio of the first thin film transistor and a channel aspect ratio of the third thin film transistor.
5 more elements
An array substrate, comprising:
- a plurality of sub-pixels disposed on the substrate and arranged in array, wherein each sub-pixel comprises a main area, a first sub-area, and a second sub-area,
- a plurality of gate lines, wherein each gate line is disposed in the sub-pixel in each row, and between the main area and the second sub-area;
- a plurality of data lines and a plurality of divided voltage lines, wherein each data line and each divided voltage line are disposed in the sub-pixel in each column, the two adjacent data lines define a pixel boundary, and the divided voltage line is disposed between two adjacent data lines;
- a pixel electrode, wherein the pixel electrode comprises a main pixel electrode disposed in the main area, a first sub-pixel electrode disposed in the first sub-area, and a second sub-pixel electrode disposed in the second sub-area;
- and
- a common electrode, wherein the common electrode and the gate line are disposed in a same layer, and the common electrode is disposed in the main area, the first sub-area, and the second sub-area;
- wherein the sub-pixel further comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the first thin film transistor is electrically connected to the first sub-pixel electrode, the second thin film transistor is electrically connected to the main pixel electrode, the third thin film transistor is electrically connected to the second sub-pixel electrode, and the fourth thin film transistor is electrically connected to the divided voltage line;
- and
- wherein a channel aspect ratio of the second thin film transistor is greater than a channel aspect ratio of the first thin film transistor and a channel aspect ratio third thin film transistor, and the channel aspect ratio of the first thin film transistor is equal to the channel aspect ratio of the third thin film transistor.
6 more elements
Dependencies are inferred from the claim text.