Chip test method, apparatus, device, and system

A chip test method, configured for testing m*n chips at m*n chip test sites, the chip test method comprising:

• coupling each of the m*n chips to one set of m sets of first signal lines of a test equipment and one set of m*n sets of second signal lines;
• determining a coupling relationship between a signal line and a tested chip coupled thereto;
• simultaneously outputting, according to the coupling relationship, a test instruction to a first signal line coupled to the tested chip, and writing data or reading data via a second signal line coupled to the tested chip;
• activating the n chip selection signal lines in sequence, simultaneously outputting a write instruction and a write address to the m sets of first signal lines, and respectively writing the data to m sets of second signal lines coupled to m chips currently controlled by a chip selection signal line, to implement a write test on m*n tested chips in n batches, wherein m tested chips are simultaneously tested in each batch;
• or
• outputting a write instruction and a write address to them sets of first signal lines in sequence, simultaneously activating the n chip selection signal lines, and respectively writing the data to n sets of second signal lines coupled to n chips currently controlled by a first signal line, to implement a write test on m*n tested chips in m batches, wherein n tested chips are simultaneously tested in each batch;
• wherein each chip is coupled to one of n chip selection signal lines of the test equipment, and each of the m*n chip test sites corresponds to a unique combination of a chip selection signal line and a first signal line coupled thereto.

A chip test apparatus, configured to test m*n chips at m*n chip test sites, the chip test apparatus comprising:

• a test solution determination module, configured to determine a coupling relationship between a signal line and a tested chip coupled thereto, wherein the test chip is included in the m*n chips, each of the m*n chips is coupled to one set of m sets of first signal lines of a test equipment and one of n chip selection signal lines, each chip is coupled to one set of m*n sets of second signal lines of the test equipment, the n chip selection signal lines respectively coupled to the m*n chips are not the same, and the first signal lines respectively coupled to the m*n chips are not the same;
• and
• a test instruction output module, configured to activate, according to the coupling relationship, a chip selection signal line coupled to the tested chip, simultaneously output a test instruction to a first signal line coupled to the tested chip, and write data or read data via a second signal line coupled to the tested chip;
• wherein the test equipment is configured to:
• activate the n chip selection signal lines in sequence, simultaneously output a write instruction and a write address to the m sets of first signal lines, and respectively write the data to m sets of second signal lines coupled to m chip test sites currently controlled by a chip selection signal line, to implement a write test on m*n tested chips in n batches, wherein m tested chips are simultaneously tested in each batch;
• or
• output a write instruction and a write address to the m sets of first signal lines in sequence, simultaneously activate the n chip selection signal lines, and respectively write the data to n sets of second signal lines coupled to n chip test sites currently controlled by a first signal line, to implement a write test on m*n tested chips in m batches, wherein n tested chips are simultaneously tested in each batch;
• wherein each chip is coupled to one of n chip selection signal lines of the test equipment, and each of the m*n chip test sites corresponds to a unique combination of a chip selection signal line and a first signal line coupled thereto.

A chip test equipment, comprising:

• n chip selection signal lines, m sets of first signal lines, and m*n sets of second signal lines;
• a memory;
• and
• a processor coupled to the memory, wherein the processor is configured to execute an instruction stored in the memory, to perform operations including:
• determining a coupling relationship between a signal line and a tested chip coupled thereto, wherein the tested chip is included in m*n chips at m*n chip test sites, each of the m*n chips is coupled to one set of the m sets of first signal lines and one set of the m*n sets of second signal lines;
• simultaneously, according to the coupling relationship, outputting a test instruction to a first signal line coupled to the tested chip, and writing data or reading data via a second signal line coupled to the tested chip;
• activating the n chip selection signal lines in sequence, simultaneously outputting a write instruction and a write address to the m sets of first signal lines, and respectively writing the data to m sets of second signal lines coupled to m chips currently controlled by a chip selection signal line, to implement a write test on m*n tested chips in n batches, wherein m tested chips are simultaneously tested in each batch;
• or
• outputting a write instruction and a write address to them sets of first signal lines in sequence, simultaneously activating the n chip selection signal lines, and respectively writing the data to n sets of second signal lines coupled to n chips currently controlled by a first signal line, to implement a write test on m*n tested chips in m batches, wherein n tested chips are simultaneously tested in each batch;
• wherein each chip is coupled to one of n chip selection signal lines of the test equipment, and each of the m*n chip test sites corresponds to a unique combination of a chip selection signal line and a first signal line coupled thereto.

A non-transitory computer readable storage medium storing a program, when being executed by a processor to cause the processor to perform operations including:

• determining a coupling relationship between a signal line and a tested chip coupled thereto, wherein the tested chip is included in m*n chips at m*n chip test sites, each of the m*n chips is coupled to one set of the m sets of first signal lines and one set of the m*n sets of second signal lines;
• simultaneously outputting, according to the coupling relationship, a test instruction to a first signal line coupled to the tested chip, and writing data or reading data via a second signal line coupled to the tested chip;
• activating the n chip selection signal lines in sequence, simultaneously outputting a write instruction and a write address to the m sets of first signal lines, and respectively writing the data to m sets of second signal lines coupled to m chips currently controlled by a chip selection signal line, to implement a write test on m*n tested chips in n batches, wherein m tested chips are simultaneously tested in each batch;
• or
• outputting a write instruction and a write address to them sets of first signal lines in sequence, simultaneously activating the n chip selection signal lines, and respectively writing the data to n sets of second signal lines coupled to n chips currently controlled by a first signal line, to implement a write test on m*n tested chips in m batches, wherein n tested chips are simultaneously tested in each batch;
• wherein each chip is coupled to one of n chip selection signal lines of the test equipment, and each of the m*n chip test sites corresponds to a unique combination of a chip selection signal line and a first signal line coupled thereto.