High speed digital data transmission
AssigneeATI Technologies ULC
InventorSaman Asgaran
Life of this patent
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Abstract
A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.
Claims20
A receiver circuit comprising:
- an analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input terminal adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level;
- and
- a non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps,
- wherein the SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.
A data processing system comprising:
- a DRAM memory;
- and
- a data processor coupled to the DRAM memory with one or more transmission lines and including respective receivers coupled to the transmission lines to receive data signals therefrom, each receiver comprising:
- an analog front end including a super source follower (SSF) amplifier having a first input terminal coupled to a respective one of the transmission lines to receive an input signal referenced to a first voltage level, a second input terminal adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level;
- and
- a non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps,
- wherein the SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.
A method comprising:
- (a) at a first circuit, receiving a signal over a transmission line from a second circuit, the signal referenced to a first voltage level and having a data rate of at least 14 Gbps;
- (b) inputting the signal to an analog front end including a super source follower (SSF) amplifier having a frequency response with a peak at a frequency approximately ⅔ of the data rate;
- (c) outputting an amplified version of the signal from the analog front end referenced to a second voltage level different from the first voltage level;
- and
- (d) inputting the amplified version of the signal to a non-linear equalizer compensate for inter-symbol interference.
Dependencies are inferred from the claim text.