US 11,533,068 B1Granted

Low intermediate frequency transmitter

AssigneeTexas Instruments Incorporated

InventorsRahul Sharma, Karthikeyan Gunasekaran, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony, Jaiganesh Balakrishnan, Sandeep Kesrimal Oswal, Visvesvaraya Pentakota

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Abstract

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

Claims24

Dependent claims

A radio frequency (RF) transmitter, comprising:

an upconverter configured to output an in-phase (I) signal and a quadrature (Q) signal;
a digital timing offset circuit coupled to the upconverter and configured to introduce a time offset between the I signal and the Q signal;
a first digital-to-analog converter (DAC) coupled to at least one of the upconverter and the digital timing offset circuit and configured to (i) receive a first clock signal and the I signal and (ii) output an analog I signal;
a second DAC coupled to at least one of the upconverter and the digital timing offset circuit and configured to (i) receive a second clock signal and the Q signal and (ii) output an analog Q signal, the first and second clock signals having a same frequency and being offset relative to each other by the time offset;
an analog timing offset removal circuit coupled to at least one of the first DAC and the second DAC and configured to remove the time offset between the analog I signal and the analog Q signal;
a first pulse shaper coupled to at least one of the first DAC and the analog timing offset removal circuit and configured to receive the analog I signal and output a pulse-shaped I signal;
a second pulse shaper coupled to at least one of the second DAC and the analog timing offset removal circuit and configured to receive the analog Q signal and output a pulse-shaped Q signal;
and
an adder coupled to the first pulse shaper and the second pulse shaper and configured to receive the pulse-shaped I and Q signals and output an intermediate frequency signal.

6 more elements

A circuit, comprising:

a first digital-to-analog converter (DAC) configured to receive an in-phase signal and having:
a first output;
a second output;
a first current source;
a first switch coupled to the first current source and to the first output;
and
a second switch coupled to the first current source and to the second output, the first and second switches being configured to receive a first clock signal;
a third switch coupled to the first output and to a common mode voltage rail;
a fourth switch coupled to the second output and to the common mode voltage rail, the third and fourth switches being configured to receive a first control signal;
a first switching bank having a first input, a second input, a third output, and a fourth output, the first input being coupled to the first output and the second input being coupled to the second output;
a first resistor coupled to the third output and to the common mode voltage rail;
a second resistor coupled to the fourth output and to the common mode voltage rail;
a second DAC configured to receive a time-advanced quadrature signal and having:
a fifth output;
a sixth output;
a second current source;
a fifth switch coupled to the second current source and to the fifth output;
and
a sixth switch coupled to the second current source and to the sixth output, the fifth and sixth switches being configured to receive a second clock signal;
a seventh switch coupled to the fifth output and to ground;
an eighth switch coupled to the sixth output and to ground, the seventh and eighth switches being configured to receive a second control signal;
and
a second switching bank having a third input, a fourth input, a seventh output, and an eighth output, the third input being coupled to the fifth output and the fourth input being coupled to the sixth output.

20 more elements

Dependencies are inferred from the claim text.