Ultra-low power adaptively reconfigurable system

A system comprising:

• an input/output (IO) device to receive a first input signal from a signal source;
• a digital subsystem comprising a memory and a central processing unit (CPU) coupled to the memory;
• a programmable analog subsystem (PASS) coupled to the IO device and to the digital subsystem, wherein the PASS comprises:
• a plurality of reconfigurable analog circuits, comprising at least one of:
• a continuous time block (CTB), or
• an analog-to-digital converter (ADC);
• a logic circuit;
• and
• an interface to communicate data with the CPU external to the PASS,
• wherein the PASS is configured to:
• in a first PASS configuration and with the digital subsystem in a sleep mode, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first PASS configuration;
• and
• change, responsive to the logic circuit processing the first output value, one or more settings of the CTB to reconfigure the PASS into a second PASS configuration with a second configuration setting without CPU involvement, wherein the second configuration setting is different than the first configuration setting.

A method comprising:

• receiving a first input signal from an input/output (IO) device by a programmable analog subsystem (PASS) coupled to the IO device, the PASS comprising a plurality of reconfigurable analog circuits, the plurality of reconfigurable analog circuits comprising at least one of (i) a continuous time block (CTB) or (ii) an analog-to-digital converter (ADC), a logic circuit, and an interface to communicate data with a central processing unit (CPU) external to the PASS;
• processing, with the PASS in a first PASS configuration, the first input signal through the plurality of reconfigurable analog circuits, wherein the plurality of reconfigurable analog circuits have a first configuration setting in the first PASS configuration;
• generating a first output value based on the first input signal;
• and
• changing, responsive to the logic circuit processing the first output value, one or more settings of the CTB to reconfigure functionality of the plurality of reconfigurable analog circuits into a second PASS configuration with a second configuration setting, wherein the second configuration setting is different than the first configuration setting.