Stacked neuromorphic devices and neuromorphic computing systems

A neuromorphic computing system comprising

• a host and a stacked neuromorphic device, wherein
• the stacked neuromorphic device includes a logic die configured to communicate with the host, a plurality of core dies stacked on the logic die, and a plurality of through silicon vias (TSVs) extending through the plurality of core dies to connect to the plurality of core dies to the logic die,
• at least one of the plurality of core dies includes at least one neuromorphic core die,
• the at least one neuromorphic core die including a synapse array connected to a plurality of row lines and a plurality of column lines, the synapse array includes a plurality of synapses configured to store weights and to perform a calculation based on the weights and an input data, and the weights are included in a plurality of layers constituting a neural network system, and
• the logic die includes a control circuit configured to provide the weights to the at least one neuromorphic core die through the TSVs and to control data transmission among the at least one neuromorphic core dies.

A stacked neuromorphic device comprising:

• a logic die configured to communicate with a host;
• core dies stacked on the logic die;
• and
• through silicon vias (TSVs) extending through the core dies to connect the core dies to the logic die,
• wherein the core dies respectively include neuromorphic core dies,
• each of the neuromorphic core dies includes a synapse array connected to a plurality of row lines and a plurality of column lines,
• the synapse array includes a plurality of synapses configured to store weights and configured to perform an accumulation operation based on results of a multiplication operation based on the weights and an input data,
• the weights are included in a plurality of layers of a neural network system,
• the logic die includes a control circuit configured to provide the weights to the neuromorphic core dies through the TSVs and to control data transmission among the neuromorphic core dies
• the neuromorphic core dies respectively include a data processor connected to the synapse array and configured to provide an accumulation result of the accumulation operation to the control circuit through the TSVs, and
• the control circuit includes an input/output interface configured to communicate with the host, and a layer controller configured to control data transmission among the neuromorphic core dies.