IPBA-driven full-depth EPBA of operational timing for circuit design

A system for detecting timing violations in a circuit design, the system comprising:

• at least one processor coupled to a memory storing physical implementation data for a circuit design having a plurality of timing paths, each path proceeding between a begin point for the path and an endpoint for the path, and each path having at least one node thereon;
• an exhaustive path-based static timing analyzer configured to perform exhaustive path-based static timing analysis (EPBA) by computing timings along EPBA paths comprising at least a subset of the timing paths in the circuit design;
• an infinite-depth path-based static timing analyzer configured to perform infinite-depth path-based static timing analysis (IPBA) of the circuit design, and configured to bound at least a subset of the EPBA paths, for which the EPBA paths lead to endpoints not converged by the exhaustive path-based static timing analyzer, by slacks computed by the infinite-depth path-based static timing analyzer;
• and
• a report generator configured to report results of the EPBA, including arrival times at endpoints analyzed by the exhaustive path-based static timing analyzer and, at least for each such endpoint not converged by the EPBA, at least one worst EPBA path leading to the corresponding endpoint, as bounded by the IPBA slacks,
• wherein the IPBA comprises:
• slotting nodes of a designated subset of the plurality of timing paths into stages;
• propagating a plurality of signals through the nodes of the plurality of timing paths stage-by-stage, in parallel, and for at least a respective one of the stages:
• computing path-based static timing analysis (PBA) timing characteristic values for each signal, of the plurality of signals, arriving at a respective node in the respective stage;
• and
• merging corresponding first and second timing characteristic values of the computed timing characteristic values by propagating from the respective node, to a subsequent node in a path shared by the respective node and the subsequent node, either
• (a) the first timing characteristic value and not the corresponding second timing characteristic value, or
• (b) a merged timing characteristic value computed based on the first and second timing characteristic values.

A non-transitory computer-readable medium storing instructions that, when executed on one or more processors, substantially contemporaneously perform both exhaustive path-based static timing analysis (EPBA) and infinite-depth path-based static timing analysis (IPBA) to analyze physical implementation data for a circuit design having a plurality of timing paths, each path proceeding between a begin point for the path and an endpoint for the path, and each path having at least one node thereon, the EPBA to compute timings along EPBA paths comprising at least a subset of the timing paths in the circuit design, wherein:

• at least a subset of the EPBA paths, for which the EPBA paths lead to endpoints not converged by the EPBA, are bounded, according to the instructions, by slacks computed by the IPBA;
• and
• results of the EPBA are reported according to the instructions, the results including arrival times at endpoints analyzed by the EPBA and, at least for each such endpoint not converged by the EPBA, at least one worst EPBA path leading to the corresponding endpoint, as bounded by the IPBA slacks,
• wherein the IPBA comprises:
• slotting nodes of a designated subset of the plurality of timing paths into stages;
• propagating a plurality of signals through the nodes of the plurality of timing paths stage-by-stage, in parallel, and for at least a respective one of the stages:
• computing path-based static timing analysis (PBA) timing characteristic values for each signal, of the plurality of signals, arriving at a respective node in the respective stage;
• and
• merging corresponding first and second timing characteristic values of the computed timing characteristic values by propagating from the respective node, to a subsequent node in a path shared by the respective node and the subsequent node, either
• (a) the first timing characteristic value and not the corresponding second timing characteristic value, or
• (b) a merged timing characteristic value computed based on the first and second timing characteristic values.