Layout context-based cell timing characterization
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh, Li Chung Hsu
Life of this patent
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Abstract
A method performed by at least one processor includes the following steps. A layout of an integrated circuit (IC) is accessed, wherein the layout has at least one cell. A context group for the cell is determined based on a layout context of the cell, wherein the context group is associated with a timing table. A timing analysis is performed on the layout to determine whether the layout complies with a timing constraint rule according to the timing table. A system including one or more processors including instructions for implementing the method and a non-transitory computer readable storage medium including instructions for implementing the method are also provided.
Claims20
A method, performed by at least one processor, comprising:
- accessing a layout of an integrated circuit (IC), the layout comprising a cell;
- recognizing a representative context group for the cell from a set of context groups based on a layout context of the cell in the layout, the representative context group being associated with a representative timing table different from timing tables of remaining context groups in the set of context groups;
- and
- performing a timing analysis on the layout to determine whether the layout complies with a timing constraint rule according to the representative timing table.
A system, comprising one or more processors and one or more programs including instructions which, when executed by the one or more processors, cause the system to:
- access a layout of an integrated circuit (IC), the layout comprising a cell;
- recognize a representative context group for the cell from a set of context groups based on a layout context of the cell in the layout, the context group being associated with a representative timing table different from timing tables of remaining context groups in the set of context groups;
- and
- perform a timing analysis on the layout to determine whether the layout complies with a timing constraint rule according to the representative timing table.
A non-transitory computer readable storage medium, comprising instructions which, when executed by a processor, perform the steps of:
- accessing a layout of an integrated circuit (IC), the layout comprising a cell;
- recognizing a representative context group for the cell from a set of context groups based on a layout context of the cell in the layout, the context group being associated with a representative timing table different from timing tables of remaining context groups in the set of context groups;
- and
- performing a timing analysis on the layout to determine whether the layout complies with a timing constraint rule according to the representative timing table.
Dependencies are inferred from the claim text.