Assessing performance of a hardware design using formal evaluation logic

A system configured to assess performance of a hardware design for an integrated circuit to complete a set of tasks, the system comprising:

• a memory configured to store:
• the hardware design;
• a formal verification tool;
• and
• a hardware monitor comprising:
• monitoring and counting logic configured to:
• monitor one or more control signals and/or data signals of an instantiation of the hardware design to identify start and completion of a symbolic task by the instantiation of the hardware design, the symbolic task representing the set of tasks;
• and
• count a number of cycles between the start and the completion of the symbolic task;
• and
• property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task;
• and
• one or more processors configured to:
• formally verify, using the formal verification tool, that the one or more formal properties are true for the hardware design;
• and
• output an indication of whether or not each of the one or more formal properties was successfully verified, the indication providing an exhaustive assessment of the performance of the instantiation of the hardware design in completing the set of tasks.