Vector generation for maximum instantaneous peak power

A system for performing operating state analysis of an integrated circuit (IC) design, comprising:

• a memory configured to store operations;
• and
• one or more processors configured to perform the operations, the operations comprising:
• simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints;
• generating a time-based waveform for each cell of the one or more cells of the IC design changing an operating state from the first operating state to the second operating state during the switching operation;
• based on the generated time-based waveform, identifying one or more operating state changes by the each cell of the one or more cells of the IC design corresponding to the operating state analysis and associated timing window and cell information;
• verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints;
• and
• generating an analysis report for a clock cycle comprising a subset of the plurality of vectors corresponding to the verified one or more operating state changes by the each cell of the one or more cells of the IC design.

A non-transitory, tangible computer-readable device having instructions stored thereon

• that, when executed by at least one computing device, causes the at least one computing device to perform operations for operating state analysis of an integrated circuit (IC) design, the operations comprising:
• simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints;
• generating a time-based waveform for each cell of the one or more cells of the IC design changing an operating state from the first operating state to the second operating state during the switching operation;
• based on the generated time-based waveform, identifying one or more operating state changes by the each cell of the one or more cells of the IC design corresponding to the operating state analysis and associated timing window and cell information;
• verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints;
• and
• generating an analysis report for a clock cycle comprising a subset of the plurality of vectors corresponding to the verified one or more operating state changes by the each cell of the one or more cells of the IC design.