Reconfigurable circuit array using instructions including a fetch configuration data portion and a transfer configuration data portion

A data processing method comprising:

• a. providing a device, the device comprising:
• i. a memory, the memory storing a plurality of instructions, each instruction including a fetch configuration data portion and a transfer configuration data portion;
• ii. a memory controller coupled to the memory, and adapted to receive instructions from the memory;
• iii. a state machine coupled within the memory controller, the state machine adapted to direct the memory controller to fetch succeeding instructions and data from the memory based upon a previous or default configuration;
• and
• iv. a back buffer coupled with the memory controller and adapted to receive instructions from the memory controller and sequentially assert each received instruction upon the memory controller, wherein the memory controller is adapted to:
• 1. Generate an output data in accordance with most recently asserted instruction;
• 2. Transfer the output data to the target in accordance with the transfer configuration data portion of the most recently asserted instruction;
• and
• 3. Fetch a next instruction in accordance with the fetch configuration data portion of the most recently asserted instruction and as directed by the state machine;
• b. communicatively coupling the device to a target circuit, the target circuit adapted to receive output data from the device;
• c. loading a first instruction of the plurality of instructions into the back buffer;
• d. asserting the first instruction from the back buffer and to the memory controller;
• e. execution by the memory controller of the first instruction;
• f. accessing in accordance with the first instruction by the memory controller of a second instruction;
• and
• g. transference of an output data in accordance with the first instruction from the memory to a target circuit.