Selective endpoint isolation for self-healing in a cache and memory coherent system

A method comprising:

• analyzing system log information to identify a location of a defective hardware component within a cache and memory coherent system, the cache and memory coherent system including multiple processing chips each hosting a different subset of a shared memory space, each hosted subset of the shared memory space corresponding to a range of logical addresses;
• and
• responsive to determining that the location of the defective hardware component corresponds to a first processing chip of the multiple processing chips, updating one or more of routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select subset of the shared memory space hosted by a corresponding one of the multiple processing chips to remove all access routes mapping logical addresses of the shared memory space to endpoints corresponding to a first range of logical addresses hosted by the first processing chip without implementing alternate access routes to data hosted by the defective hardware component.

One or more tangible computer-readable storage media encoding computer-executable instructions for executing a computer process comprising:

• analyzing system log information to identify a location of a defective hardware component within a cache and memory coherent system, the cache and memory coherent system including multiple processing chips each hosting a different subset of a shared memory space each hosted subset of the shared memory space corresponding to a range of logical addresses;
• and
• responsive to determining that the location of the defective hardware component corresponds to a first processing chip of the multiple processing chips, updating one or more of routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select subset of the shared memory space hosted by a corresponding one of the multiple processing chips to remove all access routes mapping logical addresses of the shared memory space to endpoints corresponding to a first range of logical addresses hosted by the first processing chip without implementing alternate access routes to data hosted by the defective hardware component.