Memory modules and methods of operating same

An operating method of a memory module which includes a normal memory channel and a processing memory channel, each of the normal memory channel and the processing memory channel sharing a router of a processing buffer circuit and including a memory cell array, the method comprising:

• setting an operating mode of the router to one of an extension mode or a mirror mode, based on a mode register set command received from a host;
• accessing data stored in the normal memory channel and the processing memory channel, based on an address and a command received from the host and the set operating mode of the router;
• and
• processing, at a processing circuit included in the processing buffer circuit, the accessed data based on a processing command received from the host;
• wherein the mode register set command, the address, the command, and the processing command are transmitted from the host to the memory module in compliance with a double data rate (DDR) synchronous dynamic random access memory (SDRAM) standard.

A memory module comprising:

• a processing buffer chip;
• and
• one or more DRAM chips which store data;
• wherein the one or more DRAM chips form a normal memory channel and a processing memory channel;
• wherein the processing buffer chip includes:
• a physical layer, which receives a command/address signal and a data signal from a host;
• a first memory controller and a second memory controller, which respectively access the normal memory channel and the processing memory channel based on the command/address signal;
• a processing circuit, which processes at least a portion of data stored in the normal memory channel accessed through the first memory controller and data stored in the processing memory channel accessed through the second memory controller, based on a processing command included in the data signal;
• a buffer, which stores data processed by the processing circuit;
• and
• a router, which receives the command/address signal and the data signal from the physical layer, and transmits the command/address signal and the data signal to the first memory controller and the buffer;
• and
• wherein the processing buffer circuit communicates with the host in compliance with a double data rate (DDR) synchronous dynamic random access memory (SDRAM) standard.