Decoding method, memory storage device, and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit, used to couple to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical units;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein
• the memory control circuit unit is used to respectively perform a single-frame decoding on a plurality of first data frames read from a physical unit set, and the physical unit set contains a plurality of first physical units among the plurality of physical units,
• in response to an entire decoding result of the plurality of first data frames meeting a first condition, the memory control circuit unit is further used to obtain error evaluation information related to the physical unit set, wherein the error evaluation information reflects a bit error status of the physical unit set,
• the memory control circuit unit is further used to obtain reliability information according to the error evaluation information, and
• the memory control circuit unit is further used to perform the single-frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

A memory control circuit unit, used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and the memory control circuit unit comprises:

• a host interface, used to couple to a host system;
• a memory interface, used to couple to the rewritable non-volatile memory module;
• an error detecting and correcting circuit, and
• a memory management circuit, coupled to the host interface, the memory interface, and the error detecting and correcting circuit, wherein
• the error detecting and correcting circuit is used to respectively perform a single-frame decoding on a plurality of first data frames read from a physical unit set, and the physical unit set contains a plurality of first physical units among the plurality of physical units,
• in response to an entire decoding result of the plurality of first data frames meeting a first condition, the memory management circuit is further used to obtain error evaluation information related to the physical unit set, wherein the error evaluation information reflects a bit error status of the physical unit set,
• the memory management circuit is further used to obtain reliability information according to the error evaluation information, and
• the error detecting and correcting circuit is further used to perform the single-frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

A memory storage device, comprising:

• a connection interface unit, used to couple to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical units;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein
• the memory control circuit unit is used to respectively perform a single-frame decoding on a plurality of first data frames read from a physical unit set, and the physical unit set contains a plurality of first physical units among the plurality of physical units,
• in response to an entire decoding result of the plurality of first data frames meeting a first condition, the memory control circuit unit updates reliability information and performs the single-frame decoding on a second data frame read from one of the plurality of first physical units according to the updated reliability information, and
• in response to the entire decoding result of the plurality of first data frames not meeting the first condition, the memory control circuit unit is further used to perform a multi-frame decoding on the plurality of first data frames.