Error correction circuit and method for operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKangseok Lee, Dong-min Shin, Geunyeong Yu, Bohwan Jun, Hee Youl Kwak, Hong Rak Son
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Abstract
An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.
Claims20
An error correction circuit configured to perform error correction of data stored in a memory device, the error correction circuit comprising:
- a memory configured to store at least one decoding parameter including a first graph-degree of a first variable node and a second graph-degree of a second variable node;
- and
- a processing circuit storing the first variable node and the second variable node, wherein a first number of first check nodes connected to the first variable node is different from a second number of second check nodes connected to the second variable node,
- wherein the processing circuit is configured:
- to determine the first graph-degree and the second graph-degree according to the first number and the second number;
- to determine a decoding rule for decoding of the data stored in the memory device, based on a combination of the first graph-degree and the second graph-degree;
- and
- to output corrected data based on a decoding result.
A method for operating an error correction circuit which stores variable nodes having a first graph-degree value and variable nodes having a second graph-degree value different from the first graph-degree value, the method comprising:
- performing decoding on the variable nodes having the first graph-degree value, in a first time period;
- performing decoding on the variable nodes having the second graph-degree value, in a second time period following the first time period;
- and
- outputting corrected data based on a decoding result corresponding to the variable nodes having the first graph-degree value and the variable nodes having the second graph-degree value, wherein the decoding result is determined based on a combination of the first graph-degree value and the second graph-degree value.
A method for operating an error correction circuit which includes variable nodes having a first graph-degree value and variable nodes having a second graph-degree value different from the first graph-degree value, the method comprising:
- performing decoding on the variable nodes having the first graph-degree value, in a first iteration;
- performing decoding on the variable nodes having the second graph-degree value, in a second iteration following the first iteration;
- and
- outputting corrected data based on a first decoding result corresponding to the variable nodes having the first graph-degree value and the variable nodes having the second graph-degree value, wherein the first decoding result is determined based on a combination of the first graph-degree value and the second graph-degree value.
Dependencies are inferred from the claim text.