Controller and method of operating the same
AssigneeSK hynix Inc.
InventorsSoo Jin Park, Won Hyoung Lee
Life of this patent
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Abstract
A memory system includes at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe including a plurality of unit data and parity data is stored, and a controller configured to control an operation of the semiconductor memory device. The controller performs an error correction operation on one or more unit data received from the semiconductor memory device, and generates data for recovery based on remaining data except for first and second unit data among the plurality of unit data, in response to a first error correction failure for the first unit data among the plurality of unit data and a second error correction failure for the second unit data.
Claims15
A memory system comprising:
- at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe including a plurality of unit data and parity data generated from the plurality of unit data is stored;
- and
- a controller configured to control an operation of the semiconductor memory device,
- wherein the controller performs an error correction operation on one or more unit data received from the semiconductor memory device, and generates data for recovery based on the parity data and remaining unit data except for first and second unit data among the plurality of unit data and zero data including zero bits, in response to a first error correction failure for the first unit data among the plurality of unit data and a second error correction failure for the second unit data, and
- wherein the controller generates a stripe for recovery by replacing one of the first and second unit data included in the original data stripe with the data for recovery and replacing another of the first and second unit data with the zero data.
A method of operating a controller, the method comprising:
- controlling at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe includes a plurality of unit data and parity data generated from the plurality of unit data;
- detecting an error correction failure of first and second unit data in the original data stripe;
- generating data for recovery based on the parity data and remaining unit data except for the first and second unit data among the plurality of unit data in the original data stripe;
- and
- generating a stripe for recovery by replacing one of the first and second unit data with the data for recovery and replacing another of the first and second unit data with zero data, wherein the zero data is data including zero bits.
A memory system comprising:
- a memory device including a plurality of memory blocks;
- and
- a controller configured to:
- write a data stripe to the plurality of memory blocks, the data stripe including a plurality of unit data and parity data generated from and associated with the plurality of unit data, such that data of the data stripe are respectively written to the plurality of memory blocks;
- perform an error correction operation on one or more unit data received from the plurality of memory blocks;
- when an error correction failure for first unit data among the plurality of unit data is detected, generate recovery data using the parity data and remaining unit data except for the first unit data among the plurality of unit data;
- when an error correction failure for second unit data among the plurality of unit data is detected, generate all zero data;
- select first and second memory blocks among the plurality of memory blocks in which the first and second unit data are written, respectively;
- and
- write data of the first and second memory blocks to first and second free blocks, respectively, wherein the data of the first memory block includes the recovery data instead of the first unit data, and the data of the second memory block includes the all zero data instead of the second unit data.
Dependencies are inferred from the claim text.