Technology for optimizing hybrid processor utilization

A data processing system with technology for managing threads, the data processing system comprising:

• a hybrid processor comprising (a) a big thread processing unit (TPU) that supports a first range of power settings, and (b) a small TPU that supports a second range of power settings, wherein the range for the big TPU comprises an upper bound that causes more power consumption than an upper bound of the range for the small TPU, and wherein at least one of the TPUs comprises a logical processor (LP) of a processing core that supports simultaneous multi-threading (SMT);
• hardware feedback circuitry in the hybrid processor;
• a non-transitory machine-readable medium in communication with the hybrid processor;
• and
• instructions in the machine-readable medium which, when executed by the hybrid processor, enable an operating system (OS) in the data processing system to:
• collect processor topology data from the hybrid processor;
• collect hardware feedback for at least one of the TPUs from the hardware feedback circuitry;
• and
• in response to determining that a thread is ready to be scheduled, utilize (a) an operating-preference (OP) setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread, wherein the operation of making a scheduling determination for the ready thread comprises:
• based on the OP setting for the ready thread, determining whether the ready thread has an operating preference for efficiency or an operating preference for quality of service (QOS);
• in response to determining that the ready thread has an operating preference for efficiency:
• (i) using the hardware feedback and the processor topology data to determine whether the hybrid processor comprises an idle and efficient TPU that has a busy sibling TPU, in that the idle and efficient TPU (a) is idle, (b) has a relatively high efficiency rating relative to efficiency ratings of other TPUs in the processor, and (c) has a sibling TPU that is busy;
• and
• (ii) in response to determining that the hybrid processor comprises an idle and efficient TPU that has a busy sibling TPU, selecting that idle and efficient TPU that has a busy sibling TPU to receive the ready thread;
• and
• in response to determining that the ready thread has an operating preference for QOS:
• (i) using the hardware feedback and the processor topology data to determine whether the hybrid processor comprises an idle and performant TPU that has no busy siblings, in that the idle and performant TPU (a) is idle, (b) has a relatively high performance rating relative to performance ratings of other TPUs in the processor and (c) has no busy sibling TPUs;
• and
• (ii) in response to determining that the hybrid processor comprises an idle and performant TPU that has no busy siblings, selecting that idle and performant TPU that has no busy siblings to receive the ready thread.

An apparatus comprising:

• A non-transitory machine-readable medium;
• and
• instructions in the machine-readable medium which, when executed by a hybrid processor in a data processing system, enable an operating system (OS) in the data processing system to:
• collect processor topology data from the hybrid processor, wherein the hybrid processor comprises (a) a big thread processing unit (TPU) that supports a first range of power settings, and (b) a small TPU that supports a second range of power settings, wherein the range for the big TPU comprises an upper bound that causes more power consumption than an upper bound of the range for the small TPU, and wherein at least one of the TPUs comprises a logical processor (LP) of a processing core that supports simultaneous multi-threading (SMT);
• collect hardware feedback for at least one of the TPUs from hardware feedback circuitry in the hybrid processor;
• in response to determining that a thread is ready to be scheduled, utilize (a) an operating-preference (OP) setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread;
• track running time for important threads running on TPUs other than the big TPU;
• and
• in response to determining that one of the important threads has run on one or more TPUs other than the big TPU for at least a threshold amount of time, schedule that thread on the big TPU.