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US 11,531,562 B2Granted
Systems, methods, and apparatuses for resource monitoring
AssigneeIntel Corporation
InventorsMatthew Fleming, Edwin Verplanke, Andrew Herdrich, Ravishankar Iyer
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.
Claims30
A processor comprising:
- a plurality of cores, a first core of the plurality of cores comprising multi-threaded execution circuitry to simultaneously execute instructions, the multi-threaded execution circuitry to provide a first logical processor and a second logical processor;
- an interconnect to couple the first core to a Level 3 (L3) cache;
- and
- resource management circuitry to assign a first resource management identifier (RMID) value and a first class of service (CLOS) value to the first logical processor, the resource management circuitry to track a plurality of different resource consumption metrics related to the first logical processor based on the first RMID value,
- wherein the resource management circuitry is to maintain an indication of a maximum number of RMID values to be available for association with logical processors;
- a first model-specific register (MSR) to store control data related to execution of the first logical processor, the control data comprising the first RMID value and the first CLOS value, wherein the first MSR is to store the first RMID value in a first field and to store the first CLOS value in a second field;
- cache monitoring circuitry to track cache utilization metrics associated with the first logical processor, the cache monitoring circuitry comprising:
- a second MSR to store an L3 cache occupancy value associated with the first RMID value;
- and
- a third MSR to store an event identifier (ID) in a first field to indicate an event to be monitored during execution of the first logical processor and to store the first RMID value in a second field to associate the event with the first logical processor, wherein the event relates to L3 cache occupancy.
7 more elements
A method comprising:
- providing a first logical processor and a second logical processor by multi-threaded execution circuitry of a first core, the first core comprising one of a plurality of cores coupled over an interconnect to a Level 3 (L3) cache;
- executing instructions in parallel on the first logical processor and the second logical processor;
- assigning a first resource management identifier (RMID) value and a first class of service (CLOS) value to the first logical processor;
- tracking, based on the first RMID value, a plurality of different resource consumption metrics related to the first logical processor;
- maintaining an indication of a maximum number of RMID values to be available for association with logical processors;
- storing, in a first model-specific register (MSR), control data related to execution of the first logical processor, the control data comprising the first RMID value and the first CLOS value, wherein the first MSR is to store the first RMID value in a first field and to store the first CLOS value in a second field;
- wherein one of the plurality of different resource consumption metrics comprises cache utilization metrics associated with the first logical processor, wherein tracking further comprises:
- storing, in a second MSR, an L3 cache occupancy value associated with the first RMID value;
- and
- storing, in a third MSR, an event identifier (ID) in a first field to indicate an event to be monitored during execution of the first logical processor and to store the first RMID value in a second field to associate the event with the first logical processor, wherein the event relates to L3 cache occupancy.
7 more elements
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
- providing a first logical processor and a second logical processor by multi-threaded execution circuitry of a first core, the first core comprising one of a plurality of cores coupled over an interconnect to a Level 3 (L3) cache;
- executing instructions in parallel on the first logical processor and the second logical processor;
- assigning a first resource management identifier (RMID) value and a first class of service (CLOS) value to the first logical processor;
- tracking, based on the first RMID value, a plurality of different resource consumption metrics related to the first logical processor;
- maintaining an indication of a maximum number of RMID values to be available for association with logical processors;
- storing, in a first model-specific register (MSR), control data related to execution of the first logical processor, the control data comprising the first RMID value and the first CLOS value, wherein the first MSR is to store the first RMID value in a first field and to store the first CLOS value in a second field;
- wherein one of the plurality of different resource consumption metrics comprises cache utilization metrics associated with the first logical processor, wherein tracking further comprises:
- storing, in a second MSR, an L3 cache occupancy value associated with the first RMID value;
- and
- storing, in a third MSR, an event identifier (ID) in a first field to indicate an event to be monitored during execution of the first logical processor and to store the first RMID value in a second field to associate the event with the first logical processor, wherein the event relates to L3 cache occupancy.
7 more elements
Dependencies are inferred from the claim text.