System and method for instruction mapping in an out-of-order processor

A method comprising:

• mapping instructions by mapping integer and floating-point (FP) architectural registers (ARs) of the instructions to integer and FP physical registers (PRs), respectively, based on integer mapper state and FP mapper state, respectively;
• recording, via at least one FP present indicator, presence of FP ARs used as destinations in the instructions;
• copying, periodically, the integer mapper state to integer snapshot circuitry;
• and
• copying intermittently, based on the at least one FP present indicator, the FP mapper state to FP snapshot circuitry.

A mapper configured to:

• map instructions by mapping integer and floating-point (FP) architectural registers (ARs) of instructions to integer and FP physical registers (PRs), respectively, based on integer mapper state and FP mapper state of the mapper, respectively;
• record, via at least one FP present indicator, presence of FP ARs used as destinations in the instructions;
• and
• copy, periodically, the integer mapper state to integer snapshot circuitry and to copy intermittently, based on the at least one FP present indicator, the FP mapper state to FP snapshot circuitry.

An apparatus comprising:

• means for mapping instructions by mapping integer and floating-point (FP) architectural registers (ARs) of instructions to integer and FP physical registers (PRs), respectively, based on integer mapper state and FP mapper state of the mapper, respectively;
• means for recording, via at least one FP present indicator, presence of FP ARs used as destinations in the instructions;
• means for copying, periodically, the integer mapper state to integer snapshot circuitry;
• and
• means for copying intermittently, based on the at least one FP present indicator, the FP mapper state to FP snapshot circuitry.