Processing apparatus and processing method
AssigneeShanghai Cambricon Information Technology Co., Ltd.
InventorsTianshi Chen, Shengyuan Zhou, Zidong Du, Qi Guo
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Abstract
The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.
Claims14
A processing device comprising:
- a memory configured to store data, wherein the data include data to be computed in a neural network;
- a computational circuit configured to compute the data to be computed in the neural network, including performing computations on the data to be computed in the neural network with different computation bit widths by using an adder circuit and a multiplier circuit;
- and
- a control circuit configured to control the memory and the computational circuit, including determining a type of the multiplier circuit and a type of the adder circuit of the computational circuit according to the data to be computed so as to perform computations,
- wherein the memory includes:
- an input storage circuit configured to store the data to be computed in the neural network,
- an output storage circuit configured to store a computation result,
- a neuron storage circuit configured to store neuron parameters,
- a synaptic storage circuit configured to store synaptic parameters, and
- a caching circuit configured to cache data,
- wherein the output storage circuit further includes:
- an intermediate computation result storage sub-circuit configured to store an intermediate computation result, and
- a final computation result storage sub-circuit configured to store a final computation result.
A method of using a processing device, wherein the method comprises:
- generating, by a control circuit, a control instruction, and transmitting the control instruction to a memory and a computational circuit;
- inputting, by the memory, data to be computed in a neural network into the computational circuit according to the received control instruction;
- selecting, by the computational circuit, a multiplier circuit and an adder circuit of a corresponding type in a first computation circuit according to the received control instruction;
- and
- performing, by the computational circuit, computations on the data to be computed in the neural network with different computation bit widths according to the input data to be computed and parameters of the neural network as well as the control instruction, and sending a computation result back to the memory, wherein the computational circuit uses an adder circuit, a basic multiplier, a sparse multiplier, and/or a fused vector multiplier to perform computations on the data to be computed in the neural network according to the input data to be computed and the parameters of the neural network as well as the control instruction.
Dependencies are inferred from the claim text.