Processing apparatus and processing method with dynamically configurable operation bit width

A method, comprising steps of:

• generating, by the control circuit, a control instruction, and transmitting the control instruction to a memory, a data width adjustment circuit, and an operation circuit;
• inputting, by the memory, data to be operated in a neural network into the operation circuit according to the received control instruction;
• adjusting, by the data width adjustment circuit, a width of the data to be operated in the neural network according to the received control instruction;
• and
• performing, by the operation circuit, operation of the data to be operated in the neural network with different operation bit widths according to the input data to be operated and parameters of the neural network as well as the control instruction, and sending the operation result back to the memory, wherein the memory comprises:
• an input storage circuit, configured to store the data to be operated in the neural network;
• an output storage circuit, configured to store the intermediate operation result and the final operation result;
• and
• a buffer circuit, configured to buffer the data;
• wherein the input storage circuit comprises:
• a neuron storage circuit for storing neuron parameters;
• and
• a synaptic storage circuit for storing synaptic parameters;
• the output storage circuit comprises:
• an intermediate operation result storage sub-circuit for storing the intermediate operation result;
• and
• a final operation result storage sub-circuit for storing the final operation result.