US 11,531,524 B2Granted

Magnetoresistive random-access memory (MRAM) random number generator (RNG) and a related method for generating a random bit

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHarry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Chih-Hui Weng, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang, Chia-Hsiang Chen

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Abstract

In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

Claims20

Dependent claims

A method for generating a random bit, the method comprising:

generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell a first time, wherein the RNG signal has a probability of about 0.5 to switch a resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state;
reading the first random bit from the MRAM cell;
generating a second random bit by providing the RNG signal to the MRAM cell a second time, wherein the RNG signal has a RNG value corresponding to one or more pulses configured to have a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state;
reading the second random bit from the MRAM cell;
and
determining the RNG value corresponding to the one or more pulses, wherein determining the RNG value corresponding to the one or more pulses comprises:
performing a probability trimming loop by:
setting the resistive state of the MRAM cell to the first resistive state a first time;
providing a first write signal having a first value corresponding to the one or more pulses to the MRAM cell;
after the first write signal is provided to the MRAM cell, recording the resistive state of the MRAM cell;
setting the resistive state of the MRAM cell to the first resistive state for a second time;
providing a second write signal having a second value corresponding to the one or more pulses different than the first value corresponding to the one or more pulses to the MRAM cell;
after the second write signal is provided to the MRAM cell, recording the resistive state of the MRAM cell;
repeating the probability trimming loop M times, where M is a number greater than or equal to 1;
if the first write signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state, determining the RNG value corresponding to the one or more pulses is the first value corresponding to the one or more pulses;
and
if the second write signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state, determining the RNG value corresponding to the one or more pulses is the second value corresponding to the one or more pulses.

14 more elements

An integrated chip (IC), comprising:

a random number generator (RNG) comprising:
a first set of N magnetoresistive random-access memory (MRAM) cells, wherein N is a number greater than or equal to 1, wherein one of the N MRAM cells of the first set of N MRAM cells is configured to switch between a first resistive state and a second resistive state, wherein the one of the N MRAM cells of the first set of N MRAM cells comprises a pinned layer and a free layer, wherein the one of the N MRAM cells of the first set of N MRAM cells has the first resistive state when a magnetic moment of the free layer has a first orientation, and wherein the one of the N MRAM cells of the first set of N MRAM cells has the second resistive state when the magnetic moment of the free layer has a second orientation different than the first orientation;
a memory component configured to store N RNG values, wherein one of the N RNG values has a probability of about 0.5 to switch the magnetic moment of the one of the N MRAM cells of the first set of N MRAM cells from the first orientation to the second orientation, thereby switching a resistive state of the one of the N MRAM cells of the first set of N MRAM cells from the first resistive state to the second resistive state;
a controller coupled to each of the N MRAM cells and the memory component, wherein the controller is configured to:
read the N RNG values and generate N RNG signals, respectively, wherein one of the N RNG signals comprises the one of the N RNG values;
and
provide the N RNG signals to the N MRAM cells, respectively, wherein the one of the N RNG signals is provided to the one of the N MRAM cells of the first set of N MRAM cells;
and
RNG output circuitry coupled to the N MRAM cells, wherein the RNG output circuitry is configured to read the resistive state of each of the N MRAM cells and output an N-bit random number based on the read resistive states of the N MRAM cells;
tester circuitry configured to determine the one of the N RNG values by:
providing a first write signal having a first value to the one of the N MRAM cells of the first set of N MRAM cells multiple times;
providing a second write signal having a second value different than the first value to the one of the N MRAM cells of the first set of N MRAM cells multiple times;
if the first write signal has a probability of about 0.5 to switch the magnetic moment of the one of the N MRAM cells of the first set of N MRAM cells from the first orientation to the second orientation, determining the one of the N RNG values is the first value;
and
if the second write signal has a probability of about 0.5 to switch the magnetic moment of the one of the N MRAM cells of the first set of N MRAM cells from the first orientation to the second orientation, determining the one of the N RNG values is the second value.

12 more elements

A method for generating an N-bit random number, the method comprising:

setting a resistive state of each of N magnetoresistive random-access memory (MRAM) cells to a first resistive state, wherein each of the N MRAM cells is configured to switch between the first resistive state and a second resistive state, and wherein N is a number greater than or equal to 1;
generating an N-bit random number by providing N random number generator (RNG) signals to the N MRAM cells, respectively, wherein each of the N RNG signals comprises a RNG value that has a probability of about 0.5 to switch the resistive state of each one of the N RNG signals respective MRAM cell from the first resistive state to the second resistive state;
and
determining the RNG value for one of the N MRAM cells by:
providing a first write signal having a first value to the one of the N MRAM cells multiple times;
providing a second write signal having a second value different than the first value to the one of the N MRAM cells multiple times;
if the first write signal has a probability of about 0.5 to switch the resistive state of the one of the N MRAM cells from the first resistive state to the second resistive state, determining the RNG value for the one of the N MRAM cells is the first value;
and
if the second write signal has a probability of about 0.5 to switch the resistive state of the one of the N MRAM cells from the first resistive state to the second resistive state, determining the RNG value for the one of the N MRAM cells is the second value.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/434,345Filed 7 Jun 2019 · us provisional application
Priority: 24 Sep 2018
Published: US 2020/0097255 A126 Mar 2020
Granted: 20 Dec 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 7/588
Random or pseudo-random number generators: random number generators, i.e. based on natural stochastic processes
G11C 11/1673
Auxiliary circuits: reading or sensing circuits or methods
G11C 11/1675
Auxiliary circuits: writing or programming circuits or methods
G06F
Computing and data processing