Selecting an ith largest or a pth smallest number from a set of n m-bit numbers

A processing unit configured to generate and select a number, the processing unit comprising:

• a generation logic unit, implemented in fixed function hardware circuitry, configured to perform a MSB-first iterative calculating process to generate a set of n numbers;
• a selection logic unit, implemented in fixed function hardware circuitry, configured to operate concurrently with the generation logic unit, and configured to perform a MSB-first iterative selection process to select either an ith largest or a pth smallest number from the set of n numbers, where i, p and n are integers;
• and
• an output arranged to output data indicative of the selected number,
• wherein the processing unit is configured to, in response to the selection logic unit determining that a particular one of the numbers of said set of n numbers will not be the selected number, cause the generation logic unit to halt the calculation of said particular number by said MSB-first iterative generating process after at least one of the bits of said particular number has been generated and before all of the bits of said particular number have been generated.

An integrated circuit manufacturing system comprising:

• a computer readable storage medium having stored thereon a computer readable description of an integrated circuit that describes a processing unit;
• a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the processing unit;
• and
• an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description,
• wherein the processing unit comprises:
• a generation logic unit, implemented in fixed function hardware circuitry, configured to perform a MSB-first iterative calculating process to generate a set of n numbers;
• a selection logic unit, implemented in fixed function hardware circuitry, configured to operate concurrently with the generation logic unit, and configured to perform a MSB-first iterative selection process to select either an ith largest or a pth smallest number from the set of n numbers, where i, p and n are integers;
• and
• an output arranged to output data indicative of the selected number,
• and wherein the processing unit is configured to, in response to the selection logic unit determining that a particular one of the numbers of said set of n numbers will not be the selected number, cause the generation logic unit to halt the calculation of said particular number by said MSB-first iterative generating process after at least one of the bits of said particular number has been generated and before all of the bits of said particular number have been generated.