Memory modules and memory systems having the same

A memory module comprising:

• a first plurality of terminals, comprising a plurality of command/address terminals;
• a second plurality of terminals, comprising a plurality of data terminals;
• at least one monitoring terminal;
• a buffer configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals, wherein the buffer is configured to generate buffered write data and a buffered command/address, and wherein the buffer is further configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address;
• and
• a storage and processing unit configured to store at least one portion of the buffered write data, and configured to transmit the stored buffered write data as monitoring data through the at least one monitoring terminal;
• and
• a plurality of semiconductor memory devices configured to receive and store the module data in response to the module command/address.

A memory system comprising:

• a control unit comprising:
• a processor configured to execute a program to generate an internal command, an internal address, and internal data,
• a clock signal generator configured to generate a clock signal,
• a command/address generator configured to receive the internal command and the internal address to generate a first plurality of bits of command/address, in response to the clock signal, and
• a data output unit configured to receive the internal data to generate a second plurality of bits of data;
• and
• a memory module comprising:
• a first plurality of terminals, comprising a plurality of command/address terminals,
• a second plurality of terminals, comprising a plurality of data terminals,
• at least one monitoring terminal,
• a buffer configured to receive and buffer the second plurality of bits of data applied through the data terminals and the first plurality of bits of command/address applied through the command/address terminals to generate a second plurality of bits of buffered write data and a first plurality of bits of buffered command/address, the buffer being further configured to buffer the second plurality of bits of buffered write data and the first plurality of bits of buffered command/address to generate module data and a module command/address,
• a storage and processing unit configured to store at least one portion of the second plurality of bits of buffered write data, and transmit the stored at least one portion of the second plurality of bits of buffered write data as monitoring data through the at least one monitoring terminal, and
• a plurality of semiconductor memory devices configured to receive and store the module data in response to the module command/address.