Data transfer in port switch memory
AssigneeMicron Technology, Inc.
InventorFrank F. Ross
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
Claims20
An apparatus, comprising:
- a first number of memory devices coupled to a host;
- and
- a second number of memory devices coupled to the first number of memory devices via a controller, wherein the controller is configured to receive a first number of commands from the host via a register clock driver (RCD) and send the first number of commands to the first number of devices, via the RCD, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host in response to receiving the first number of commands, wherein the controller is configured to receive a second number of commands from the host via the RCD and send the second number of commands to the first number of devices, via the RCD, and to the second number of devices, and wherein the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices via the controller in response to receiving the second number of commands.
An apparatus, comprising:
- a register clock driver (RCD);
- a controller coupled to the RCD and configured to receive commands from a host via the RCD;
- a first number of memory devices coupled to the controller;
- and
- a second number of memory devices couplable to a host and coupled to the controller, wherein the controller is configured to receive a first command from the host via the RCD and execute the first command on one of the second number of memory devices by sending the first command from the controller to the one of the second number of memory devices via the RCD and transfer data from the second number of memory devices in response to receiving the first command.
A method, comprising:
- sending a first ready/busy signal from a controller of a dual in-line memory module (DIMM) to a host indicating the DIMM is ready to receive commands from the host;
- receiving a first command from the host at the controller based at least in part on sending the signal, wherein the first command is sent from the host to a register clock driver (RCD) and from the RCD to the controller and wherein the first command includes instructions to send data from a first memory device of the DIMM to the host;
- and
- executing the first command on a first memory device of the DIMM by sending the command from the controller to the first memory device via the RCD and transferring data from the first memory device, wherein the first memory device is a DRAM memory device.
Dependencies are inferred from the claim text.