Scalable memory system protocol supporting programmable number of levels of indirection
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
Life of this patent
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Abstract
A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
Claims20
A system, comprising:
- a memory device configured to receive a packet comprising a payload, wherein a portion of the payload comprises an indication of a number of levels of indirection separating a first address of a memory component from a final address of the memory component, and wherein the first address and the final address are associated with the payload, wherein the number of levels of indirection corresponds to one or more pointers associated with performing one or more operations via the memory component, and wherein the one or more operations comprise one or more read operations, one or more write operations, or any combination thereof;
- and
- an array configured to be accessed by the memory device in response to the memory device receiving the packet, wherein the array is accessed by the memory device based at least in part on the one or more pointers.
A method, comprising:
- receiving, via a processor, a packet comprising a payload, wherein a portion of the payload comprises an indication of a number of levels of indirection separating a first address of a memory component from a final address of the memory component, and wherein the first address and the final address are associated with the payload, wherein the number of levels of indirection corresponds to one or more pointers associated with performing one or more operations via the memory component, and wherein the one or more operations comprise one or more read operations, one or more write operations, or any combination thereof;
- and
- accessing, via the processor, the memory component in response to receiving the packet, wherein the memory component is accessed based at least in part on the one or more pointers.
A non-transitory computer-readable medium comprising computer-executable instructions that, when executed, are configured to cause at least one processor to perform operations comprising:
- receiving a packet comprising a payload, wherein a portion of the payload comprises an indication of a number of levels of indirection separating a first address of a memory component from a final address of the memory component, and wherein the first address and the final address are associated with the payload, wherein the number of levels of indirection corresponds to one or more pointers associated with performing one or more operations via the memory component, and wherein the one or more operations comprise one or more read operations, one or more write operations, or any combination thereof;
- and
- accessing the memory component in response to receiving the packet, wherein the memory component is accessed based at least in part on the one or more pointers.
Dependencies are inferred from the claim text.