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US 11,531,471 B2Granted
Memory circuit and memory repair method thereof
AssigneeNS Poles Technology Corp.
InventorChuang Lung Chiu
Life of this patent
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Abstract
A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.
Claims12
A memory repair method, comprising:
- (A) selecting a first row from a first memory array according to a first address data, wherein said first row has a plurality of general bits divided into a plurality of groups;
- (B) selecting a second row from a second memory array according to said first address data, wherein said second row has a plurality of flag bits for indicating whether said plurality of groups have defective bits, a plurality of address bit sets for storing a plurality of defective bit addresses, and a plurality of spare bits for replacing said defective bits, and wherein said plurality of defective bit addresses are relative addresses of said defective bits in said plurality of groups;
- (C) generating a column address according to a second address data;
- (D) detecting a flag bit corresponding to said column address, and obtaining a corresponding defective bit address from said plurality of address bit sets if said corresponding flag bit has a first-state data;
- and
- (E) selecting one of said plurality of spare bits to replace a defective bit corresponding to said corresponding defective bit address.
3 more elements
A memory circuit, comprising:
- a first memory, including a first memory array, wherein each row of said first memory array has a plurality of general bits divided into a plurality of groups;
- and
- a second memory, including a second memory array, wherein each row of said second memory array has a plurality of flag bits for indicating whether said plurality of groups have defective bits, a plurality address bit sets for storing a plurality of defective bit addresses, and a plurality of spare bits for replacing said defective bits;
- wherein if a flag bit has a first-state data, it indicates that a corresponding group has a defective bit, and if said flag bit has a second-state data, it indicates that said corresponding group is free of a defective bit;
- wherein said plurality of defective bit addresses are relative addresses of said defective bits in said plurality of groups.
2 more elements
Dependencies are inferred from the claim text.