Current-mode feedforward ripple cancellation

An apparatus comprising:

• a first transistor having a first gate, a first source and a first drain, the first source coupled to an input voltage terminal;
• an error amplifier configured to compare a voltage at the first drain to a reference signal (Vref), and provide an error signal at an error amplifier output responsive to the comparison;
• a buffer having a buffer input and a buffer output, the buffer input coupled to the error amplifier output, the buffer output coupled to the first gate;
• and
• a current-mode feedforward ripple canceller (CFFRC) having a CFFRC input and a CFFRC output, the CFFRC output coupled to the first gate, and the CFFRC input coupled to the input voltage terminal, the CFFRC including:
• a capacitor coupled to a ground terminal;
• a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal configured to receive a bias voltage, and the second resistor terminal coupled to the capacitor;
• a differential amplifier having a second amplifier output, a third amplifier input and a fourth amplifier input, the third amplifier input coupled to the capacitor;
• a second transistor having a second gate, a second source and a second drain, the second gate and the second drain coupled to the fourth amplifier input, and the second source coupled to the input voltage terminal;
• and
• a third transistor having a third gate, a third source and a third drain, the third gate coupled to the second amplifier output, and the third source coupled to the fourth amplifier input;
• wherein the CFFRC is configured to provide, at the CFFRC output, a current representing a voltage ripple on a signal at the input voltage terminal.

A system, comprising:

• a low dropout regulator (LDO) configured to provide a regulated output voltage (VOUT) at an output voltage terminal responsive to on an input voltage (VIN) at an input voltage terminal,
• wherein the LDO includes:
• a first transistor having a first gate, a first source and a first drain, the first source coupled to the input voltage terminal;
• an error amplifier configured to compare VOUT to a reference signal (Vref) and provide an error signal at an error amplifier output responsive to the comparison;
• a buffer having a buffer input and a buffer output, the buffer input coupled to the error amplifier output, and the buffer output coupled to the first gate;
• and
• a current-mode feedforward ripple canceller (CFFRC) including:
• a capacitor coupled to a ground terminal;
• a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal configured to receive a bias voltage, and the second resistor terminal coupled to the capacitor;
• a differential amplifier having a second amplifier output, a third amplifier input and a fourth amplifier input, the third amplifier input coupled to the capacitor;
• a second transistor having a second gate, a second source and a second drain, the second gate and the second drain coupled to the fourth amplifier input, and the second source coupled to the input voltage terminal;
• and
• a third transistor having a third gate, a third source and a third drain, the third gate coupled to the second amplifier output, and the third source coupled to the fourth amplifier input.