Interleaved testing of digital and analog subsystems with on-chip testing interface
AssigneeQUALCOMM Incorporated
InventorPraveen Raghuraman
Life of this patent
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Abstract
The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.
Claims13
An apparatus for interleaved on-chip testing, comprising:
- a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP);
- a built-in self-test (BIST) controller in communication with the MTAP, a phase locked loop, and a memory;
- and
- a multiplexer in communication with the memory and in communication with the phase locked loop through an AND gate.
An apparatus for interleaved on-chip testing, comprising:
- means for merging a test setup involving a system-on-chip test access port (SoC TAP) communicating with a memory test access port (MTAP);
- means for communicating with the MTAP and a memory;
- means for communicating with the memory and a phase locked loop;
- and
- a multiplexer in communication with the memory and in communication with the phase locked loop through an AND gate.
Dependencies are inferred from the claim text.