IGBT/MOSFET fault protection
AssigneeSemiconductor Components Industries, LLC
InventorTaesung Kwon
Life of this patent
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Abstract
A circuit for detecting faults affecting a power transistor comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The power transistor is turned on and off by assertion and de-assertion, respectively, of an input signal. The conditioning circuit produces a conditioned gate voltage signal from a gate voltage of the power transistor. The first fault status circuit asserts a first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval after the assertion of the input signal. The fault signaling circuit asserts a fault signal in response to the first fault indication being asserted, and de-asserting the fault signal in response to the input signal being de-asserted.
Claims18
A circuit configured to detect faults, the circuit comprising:
- a conditioning circuit configured to produce a conditioned gate voltage signal according to a gate voltage of a power transistor by;
- voltage dividing a gate voltage signal indicating the gate voltage, and
- low-pass filtering a result of a buffering of the voltage-divided gate voltage signal;
- a first fault status circuit configured to produce a first fault indication by:
- performing a comparison of the conditioned gate voltage signal to a first fault reference voltage, and
- asserting the first fault indication in response to the comparison indicating that the conditioned gate voltage signal is greater than the first fault reference voltage during a first interval that begins at an assertion of an input signal,
- wherein the first fault reference voltage is set according to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor;
- and
- a fault signaling circuit configured to produce a fault signal by:
- determining a second interval having a pre-determined duration and starting at a de-assertion of the input signal,
- asserting the fault signal in response to the first fault indication being asserted outside the second interval, and
- resetting the fault signal during the second interval,
- wherein assertion of the input signal indicates that the power transistor is to be turned on, and de-assertion of the input signal indicates that the power transistor is to be turned off.
A circuit configured to detect faults, the circuit comprising:
- a gate voltage signal input configured to receive a gate voltage signal indicating a gate voltage of a power transistor;
- an input signal input configured to receive an input signal used to control the gate voltage of the power transistor;
- a conditioning circuit configured to produce a conditioned gate voltage signal according to the gate voltage signal by:
- voltage dividing the gate voltage signal, and
- low-pass filtering a buffering of the voltage-divided gate voltage signal;
- a first fault status circuit configured to produce a first fault indication according to the input signal and the conditioned gate voltage signal, the first fault indication indicating an over-current fault, a hard switching fault, or both, the first fault status circuit comprising:
- a comparator having a positive input coupled to the conditioned gate voltage signal and a negative input coupled to a first fault reference voltage, the first fault reference voltage being determined according to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor;
- and
- a fault signaling circuit configured to produce a fault signal by:
- generating a pulse having a duration equal to a second interval by asserting the pulse for the second interval in response to a de-assertion of the input signal, de-asserting the fault signal in response to the pulse being asserted, and asserting the fault signal in response to the first fault indication being asserted when the pulse is not asserted.
A method of detecting faults, the method comprising:
- receiving an input signal used to control a gate voltage of a power transistor;
- receiving a gate voltage signal corresponding to the gate voltage;
- generating a conditioned gate voltage signal using the gate voltage signal by:
- voltage dividing the gate voltage signal, and
- low-pass filtering a buffering of the voltage-divided gate voltage signal;
- performing a first comparison of the conditioned gate voltage signal to a first fault reference voltage, the first fault reference voltage being set to a value corresponding to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor;
- determining a first time period having a first predetermined duration and starting at an assertion of the input signal,
- determining a second time period having a second predetermined duration and starting at a de-assertion of the input signal,
- in response to the first comparison indicating that the conditioned gate voltage signal is greater than the first fault reference voltage:
- asserting a fault signal when the indication occurs during the first time period, and not asserting the fault signal when the indication occurs during the second time period;
- and
- de-asserting the fault signal during the second time period.
Dependencies are inferred from the claim text.