Systems and method for a low power correlator architecture using distributed arithmetic
AssigneeThe MITRE Corporation
InventorRishi Yadav
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Abstract
Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.
Claims7
An electronic device for implement a finite impulse response filter, the device comprising:
- a plurality of bit-level multiply and accumulate circuits, wherein each bit-level multiply and accumulate circuit corresponds to a single bit of a plurality of bits, wherein the plurality of bits are associated with a data sample, and wherein each bit of plurality of bits has a position associated with it with respect to the data sample;
- a plurality of shifters configured to operate on a plurality of bit-level results generated by the plurality of bit-level multiply and accumulate circuits, wherein the plurality of shifters shift each result of the plurality of results based on the position of the bit associated with each bit-level multiply and accumulate circuit, and wherein the plurality of shifters are configured such that a plurality of results from each of the shifters when accumulated generate a finite impulse response result.
Dependencies are inferred from the claim text.