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US 11,527,631 B2Granted
Memory cells having electrically conductive nanodots and apparatus having such memory cells
AssigneeMicron Technology, Inc.
InventorNirmal Ramaswamy
Life of this patent
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Abstract
Memory cells having a first dielectric between a charge storage material and a semiconductor, conductive nanodots between the charge storage material and a control gate, and a second dielectric between the control gate and the conductive nanodots.
Claims21
A memory cell, comprising:
- a tunnel dielectric comprising silicon dioxide overlying a semiconductor material;
- a silicon-containing charge storage material overlying the tunnel dielectric;
- a silicon oxynitride barrier overlying the silicon-containing charge storage material;
- metal-containing nanodots overlying the silicon oxynitride barrier;
- an intergate dielectric overlying the metal-containing nanodots;
- a control gate overlying the intergate dielectric;
- and
- source/drain regions in the semiconductor generally adjacent the tunnel dielectric.
5 more elements
A memory device, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- and
- a controller for access of the array of memory cells;
- wherein each memory cell of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises:
- a tunnel dielectric overlying a semiconductor material;
- a silicon-containing charge storage material overlying the tunnel dielectric;
- a nitridized barrier overlying the silicon-containing charge storage material;
- a plurality of nanodots overlying the nitridized barrier, wherein the plurality of nanodots comprise an elemental metal;
- an intergate dielectric overlying the plurality of nanodots;
- a control gate overlying the intergate dielectric;
- a first source/drain region in the semiconductor material generally adjacent one end of the tunnel dielectric;
- and
- a second source/drain region in the semiconductor material generally adjacent an opposing end of the tunnel dielectric;
- and
- wherein, for each memory cell of the particular string of series-connected memory cells, at least one source/drain region of that memory cell, selected from a group consisting of its first source/drain region and its second source/drain region, is connected to a source/drain region of an adjacent memory cell of the particular string of series-connected memory cells.
12 more elements
A memory device, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a plurality of data lines;
- and
- a controller for access of the array of memory cells;
- wherein each data line of the plurality of data lines corresponds to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises a respective first memory cell selectively connected to a source and a respective last memory cell selectively connected to its respective data line;
- wherein each memory cell of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises:
- a tunnel dielectric overlying a silicon-containing semiconductor material;
- a silicon-containing charge storage material overlying the tunnel dielectric;
- a nitridized barrier overlying the silicon-containing charge storage material;
- a plurality of nanodots overlying the nitridized barrier, wherein the plurality of nanodots comprise an elemental metal;
- an intergate dielectric overlying the plurality of nanodots;
- a control gate overlying the intergate dielectric;
- a first source/drain region in the semiconductor material generally adjacent one end of the tunnel dielectric;
- and
- a second source/drain region in the semiconductor material generally adjacent an opposing end of the tunnel dielectric.
13 more elements
Dependencies are inferred from the claim text.