An interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages;
- wherein N is a non-prime positive integer, and wherein M is a positive integer equal to, or higher than, two;
- wherein the M stages include a first stage and a last stage and wherein each stage includes switching elements having, each, respective input pins and respective output pins;
- wherein the input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals;
- wherein, the input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing, each, respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage;
- whereby the interconnection network is operable to route, on the basis of routing commands applied to the switching elements, N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals;
- characterized in that M denotes a number of given submultiples of N whose product is equal to N;
- wherein each stage is associated with a respective submultiple of said M given submultiples of N, and includes Si switching elements, each having smi respective input pins and smi respective output pins, wherein Si=N/smi, wherein smi denotes said respective submultiple associated with said stage, and wherein i denotes said stage and is a positive integer comprised between one and M;
- wherein each switching element is configured to:
- receive, at the smi respective input pins, smi respective input values;
- and
- provide at the smi respective output pins, on the basis of a respective routing command applied to said switching element, smi respective output values corresponding to, or circularly shifted with respect to, said smi respective input values received at the smi respective input pins;
- wherein the interconnection sub-networks are not connected to each other;
- wherein the interconnection network includes sm1interconnection sub-networks for routing, each, N/sm1 respective input values from N/sm1 respective output pins of the switching elements of the first stage to N/smi respective input pins of the switching elements of the last stage;
- wherein sm1 denotes the submultiple, among said M given submultiples of N, which is associated with the first stage;
- and
- wherein at least one of:
- (i) the stages are arranged, from the first stage to the last stage, according to a decreasing or increasing order of said M given submultiples of N;
- (ii) the stages are arranged, from the first stage to the last stage, according to a decreasing order of said M given submultiples of N, whereby the first stage is associated with the greatest submultiple among said M given submultiples of N;
- (iii) the interconnection network includes three or more stages thereby resulting in M being equal to, or higher than, three;
- wherein each interconnection sub-network includes, at each stage different than the first and the last stages,
- N
- ∏
- k
- =
- 1
- i
-
-
- sm
- k
- switching elements of said stage, wherein i denotes said stage and is a positive integer comprised between two and M−1;
- and wherein, at each stage different than the first and the last stages, the switching elements of said stage included in each interconnection sub-network have, each,
- the smi respective input pins connected, in a hardwired fashion, to respective output pins of smi respective switching elements of an immediately previous stage, and
- the smi respective output pins connected, in a hardwired fashion, to respective input pins of smi respective switching elements of an immediately successive stage;
- (iv) N is different from a power of two;
- or
- (v) each switching element includes smi respective multiplexers, each of which is:
- connected to all the smi respective input pins of said switching element;
- connected to a respective output pin of the smi respective output pins of said switching element;
- and
- operable to connect the respective output pin to one of said smi respective input pins of the switching element, depending on the respective routing command applied to said switching element.