Variable voltage bit line precharge
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAtul Katoch, Adrian Earle
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.
Claims20
A memory device, comprising:
- an array of memory cells;
- a bit line connected to the memory cells;
- a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level;
- a bit line precharge circuit having an input terminal configured to receive the power supply voltage at the first voltage level, wherein the bit line precharge circuit is configured to select a second voltage level lower than the first voltage level and precharge the bit line to the second voltage level;
- and
- a precharge controller configured to selectively control the bit line precharge circuit to connect the bit line to the first voltage level for a first predetermined time period, and to connect the bit line to the second voltage level for a second predetermined time period that is shorter than the first predetermined time period.
A method for operating a memory device, comprising:
- controlling a first switch of a first power header to selectively connect a plurality of bit lines of a memory array directly to a power supply voltage terminal for a first predetermined time period;
- controlling a second switch of a second power header to selectively connect the plurality of bit lines to the power supply voltage terminal via a first trim device for a second predetermined time period that is shorter than the first predetermined time period.
A memory device, comprising:
- an array of memory cells;
- a bit line connected to the memory cells;
- a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level;
- a bit line precharge circuit including:
- an input terminal configured to receive the power supply voltage at the first voltage level;
- a first power header having a first switch configured to selectively connect the bit line directly to the power supply voltage terminal;
- a second power header having a trim device and a second switch configured to selectively connect the bit line to the power supply voltage terminal via the trim device;
- and
- a precharge controller configured to actuate the first switch to selectively connect the bit line directly to the power supply voltage terminal for the first predetermined time period, and to actuate the second switch to selectively connect the bit line to the power supply voltage terminal via the trim device for the second predetermined time period.
Dependencies are inferred from the claim text.