US 11,515,873 B2Granted

Semiconductor device and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsHajime Kimura, Yoshiyuki Kurokawa

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Abstract

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

Claims12

Dependent claims

A semiconductor device comprising a first circuit, the first circuit comprising:

a switching circuit comprising:
a first transistor comprising a first gate and a second gate;
a second transistor comprising a third gate and a fourth gate;
and
a first inverter circuit;
and
a second inverter circuit, a third inverter circuit, and a fourth inverter circuit,
wherein the first gate of the first transistor is electrically connected to an input terminal of the first inverter circuit,
wherein the third gate of the second transistor is electrically connected to an output terminal of the first inverter circuit,
wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the second inverter circuit,
wherein one of a source and a drain of the second transistor is electrically connected to an output terminal of the third inverter circuit,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to an input terminal of the fourth inverter circuit,
wherein the switching circuit is configured to change time from output of a signal from the output terminal of the second inverter circuit to input of the signal to the input terminal of the fourth inverter circuit in response to a potential of the second gate of the first transistor, and
wherein the switching circuit is configured to change time from output of a signal from the output terminal of the third inverter circuit to input of the signal to the input terminal of the fourth inverter circuit in response to a potential of the fourth gate of the second transistor.

11 more elements

A semiconductor device comprising a first circuit, the first circuit comprising:

a switching circuit comprising:
a first transistor comprising a first gate and a second gate;
a second transistor comprising a third gate and a fourth gate;
and
a first inverter circuit;
and
a second inverter circuit and a third inverter circuit,
wherein the first gate of the first transistor is electrically connected to an input terminal of the first inverter circuit,
wherein the third gate of the second transistor is electrically connected to an output terminal of the first inverter circuit,
wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the second inverter circuit,
wherein one of a source and a drain of the second transistor is electrically connected to an output terminal of the third inverter circuit,
wherein the other of the source and the drain of the first transistor is electrically connected to a first output terminal,
wherein the switching circuit is configured to change time from output of a signal from the output terminal of the second inverter circuit to input of the signal to the first output terminal in response to a potential of the second gate of the first transistor, and
wherein the switching circuit is configured to change time from output of a signal from the output terminal of the third inverter circuit to input of the signal to the first output terminal in response to a potential of the fourth gate of the second transistor.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/449,595Filed 24 Jun 2019
Priority: JP JP2018-12412229 Jun 2018
Published: US 2020/0007114 A12 Jan 2020
Granted: 29 Nov 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification29 codes

H03K 17/693
The devices being field-effect transistors: switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 19/003
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: modifications for increasing the reliability for protection
G06N 3/04
Neural networks: architecture, e.g. interconnection topology
G06N 3/048
Architecture, e.g. interconnection topology: activation functions