Low temperature bonded structures
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsCyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
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Abstract
Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
Claims22
A microelectronic assembly, comprising:
- a first substrate having a first bonding surface;
- a first metallic feature disposed at the first bonding surface of the first substrate, and having a first conductive material disposed on a surface of the first metallic feature;
- a second substrate having a second bonding surface;
- the second bonding surface bonded to the bonding surface of the first substrate;
- a second metallic feature disposed at the second bonding surface, and having a second conductive material disposed on a surface of the second metallic feature, wherein the second metallic feature is bonded to the first metallic feature;
- and
- an alloy mass disposed between the first metallic feature and the second metallic feature, the alloy mass comprising an alloy of the first and the second conductive materials, wherein a concentration of the first conductive material and a concentration of the second conductive material of the alloy mass is non-linear throughout the alloy mass.
A microelectronic assembly, comprising:
- a first substrate having a first surface with a first conductive interconnect structure;
- a second substrate having a second surface with a second conductive interconnect structure, the first surface bonded to the second surface and the first conductive interconnect structure bonded to the second conductive interconnect structure;
- and
- an electrically conductive alloy mass coupling the first conductive interconnect structure to the second conductive interconnect structure, wherein the conductive alloy mass includes a first material, a second material, and a third material, wherein a concentration of the first material, a concentration of the second material, and a concentration of the third material is non-linear throughout the alloy mass.
A microelectronic assembly, comprising:
- a first substrate having a first surface with a first conductive structure;
- a second substrate having a second surface with a second conductive structure;
- the first substrate intimately bonded to the second substrate and the first conductive structure bonded to the second conductive structure;
- and
- an electrically conductive alloy region coupling the first conductive structure to the second conductive structure, wherein the conductive alloy region includes a first material and a second material, and wherein a volume of the first material or a volume of the second material is less than 10% of a volume of the first conductive structure and the second conductive structure combined.
A microelectronic assembly, comprising:
- a first substrate having a first surface with a first conductive structure, a portion of e first conductive structure comprising a first conductive material;
- a second substrate having a second surface with a second conductive structure, the first surface of the first substrate intimately bonded to the second surface of the second substrate and the first conductive structure bonded to the second conductive structure;
- and
- an electrically conductive alloy region coupling the first conductive structure to the second conductive structure, wherein the alloy region includes the first conductive material, the first conductive material having a higher melting point than a melting point of portions of the first conductive structure or the second conductive structure.
Dependencies are inferred from the claim text.