US 11,508,426 B1 · Memory device, memory cell arrangement, and methods thereof

Abstract

Various aspects relate to a memory cell arrangement including: a field-effect transistor based capacitive memory cell including a memory element, wherein a memory state of the memory element defines a first memory state of the field-effect transistor based capacitive memory cell and wherein a second memory state of the memory element defines a second memory state of the field-effect transistor based capacitive memory cell; and a memory controller configured to, in the case that a charging state of the field-effect transistor based capacitive memory cell screens an actual threshold voltage state of the field-effect transistor based capacitive memory cell, cause a destructive read operation to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, residing in the first memory state or in the second memory state.

Claims20

Dependent claims

A memory device, comprising:

a memory controller configured to cause a destructive read operation to read a field-effect transistor based capacitive memory cell, the destructive read operation comprising:
supplying a set of write voltages to the field-effect transistor based capacitive memory cell to switch the field-effect transistor based capacitive memory cell from a first memory state into a second memory state;
and, subsequently,
reading the field-effect transistor based capacitive memory cell and determining, based on the reading, whether the memory cell is in a first screened threshold voltage state or in a second screened threshold voltage state to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, initially written in the first memory state associated with the first screened threshold voltage state or initially written in the second memory state associated with the second screened threshold voltage state.

1 more element

A memory cell arrangement comprising:

a field-effect transistor based capacitive memory cell comprising a memory element, wherein a memory state of the memory element defines a first memory state of the field-effect transistor based capacitive memory cell and wherein a second memory state of the memory element defines a second memory state of the field-effect transistor based capacitive memory cell;
and
a memory controller configured to, in the case that a charging state of the field-effect transistor based capacitive memory cell screens an actual threshold voltage state of the field-effect transistor based capacitive memory cell, cause a destructive read operation to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, residing in the first memory state or in the second memory state.

Dependencies are inferred from the claim text.

Memory device, memory cell arrangement, and methods thereof

Life of this patent

Memory device, memory cell arrangement, and methods thereof

Life of this patent

Abstract

Claims20