Error detection using vector processing circuitry

A method of compiling a sequence of instructions for execution by a data processing apparatus comprising scalar processing circuitry to perform scalar processing of scalar operands and vector processing circuitry to perform vector processing comprising a plurality of lanes of processing performed on vector operands comprising a plurality of data elements;

• the method comprising:
• receiving a first sequence of instructions defining main processing to be executed by the data processing apparatus, the main processing comprising main scalar processing to be executed using the scalar processing circuitry;
• and
• mapping the first sequence of instructions to a second sequence of instructions comprising instructions for controlling the data processing apparatus to execute at least:
• the main processing;
• checker processing executed using at least one lane of said plurality of lanes, the checker processing comprising operations corresponding to at least part of the main processing;
• and
• an error detection operation dependent on a comparison of an outcome of said at least part of the main processing and an outcome of the checker processing.

A data processing apparatus comprising:

• scalar processing circuitry to perform scalar processing of scalar operands;
• vector processing circuitry to perform vector processing comprising a plurality of lanes of processing performed on vector operands comprising a plurality of data elements;
• and
• control circuitry to control the vector processing circuitry to perform checker processing using at least one lane of said plurality of lanes, the checker processing comprising operations corresponding to at least part of main processing comprising main scalar processing processed on the scalar processing circuitry;
• and
• error detection circuitry to perform error detection in dependence on a comparison of an outcome of said at least part of the main processing and an outcome of the checker processing.