Phase prediction demodulator circuits and related method

A system comprising:

• a comparator circuit with a comparator input and a comparator output, the comparator input adapted to receive an input signal that is modulated with data, the comparator circuit operable to output, responsive to the input signal, a comparator signal having rising edges and falling edges;
• and
• a demodulator circuit with a demodulator input and a demodulator output, the demodulator input coupled to the comparator output, the demodulator circuit operable to:
• determine a first count value based on a first period between a first rising edge and a second rising edge of the comparator signal;
• determine a second count value based on a second period between a first falling edge and a second falling edge of the comparator signal;
• generate a data capture clock based on the first count value in response to the second count value satisfying a threshold;
• and
• generate a demodulated signal based on the data capture clock and the input signal.

A method comprising:

• resetting a first counter in response to a first rising edge of a signal, the first rising edge to identify a start bit of a bit stream at a first time;
• resetting a second counter in response to a first falling edge of the signal at a second time;
• determining a first count value of the first counter in response to a second rising edge of the signal at a third time;
• and
• in response to a second count value of the second counter satisfying a threshold, adjusting a phase of a data capture clock from a first phase to a second phase based on the first count value.

An apparatus comprising:

• a comparator circuit with a first comparator output and a second comparator output;
• a first counter circuit with a first counter input and a first counter output, the first counter input coupled to the first comparator output;
• a second counter circuit with a second counter input and a second counter output, the second counter input coupled to the second comparator output;
• a data capture clock circuit with a first input, a second input, and a first output, the first input coupled to the first counter output, the second input coupled to the second counter output;
• and
• a demodulator circuit with a first demodulator input, a second demodulator input, and a third demodulator input, the first demodulator input coupled to the first counter output, the second demodulator input coupled to the second counter output, the third demodulator input coupled to the first output.