High-speed data transmitting/receiving system and method of removing simultaneous switching noise and inter-symbol interference

A transmitter used in a data transmitting/receiving system comprising:

• a data mapping unit configured to map 2-bit input data to one of codes, wherein a first voltage level of a first signal line, a second voltage level of a second signal line, and a third voltage level of a third signal line are set in each of the codes;
• and
• a transmit driver configured to output signals corresponding to the input data through the first signal line, the second signal line, and the third signal line which respectively have the first voltage level, the second voltage level and the third voltage level corresponding to the mapped code,
• wherein each of the first voltage level, the second voltage level and the third voltage level is ‘+1’, ‘0’ or ‘−1’, a number of signal line having a voltage level of ‘+1’ is the same as a number of signal line having a voltage level of ‘−1’,
• wherein IVSS0=0.5*(IVSS+1+IVSS−1) so that the current flowing through a ground line is constant regardless of the input data, and
• wherein IVSS−1 is the current flowing through the ground line per voltage level of ‘−1’, IVSS+1 is the current flowing through the ground line per voltage level of ‘+1’, and IVSS0 is the current flowing through the ground line per voltage level of ‘0’.

A receiver which receives signals from a transmitter which maps 2-bit input data to one of codes in which a first voltage level of a first signal line, a second voltage level of a second signal line, and a third voltage level of a third signal line are set, and outputs the signals corresponding to the input data through the first signal line, the second signal line, and the third signal line which respectively have the first voltage level, the second voltage level, and the third voltage level corresponding to the mapped code, wherein even when the input data is changed, none of the first voltage level, the second voltage level, and the third voltage level is transitioned from ‘+1’ to ‘−1’ or from ‘−1’ to ‘+1’, and a number of signal line having a voltage level of ‘+1’ is the same as a number of signal line having the voltage level of ‘−1’, the receiver comprising:

• a first differential amplifier configured to receive a voltage of a first signal transmitted through the first signal line and an average voltage of voltages of the signals;
• a second differential amplifier configured to receive a voltage of a second signal transmitted through the second signal line and the average voltage of the voltages of the signals;
• a third differential amplifier configured to receive a voltage of a third signal transmitted through the third signal line and the average voltage of the voltages of the signals;
• a first multi-input differential amplifier configured to receive outputs of the first differential amplifiers, outputs of the second differential amplifiers, and reference voltages;
• a second multi-input differential amplifier configured to receive outputs of the second differential amplifiers, outputs of the third differential amplifiers, and the reference voltages;
• a third multi-input differential amplifier configured to receive outputs of the third differential amplifiers, outputs of the first differential amplifiers, and the reference voltages;
• a first sampler configured to sample outputs of the first multi-input differential amplifier;
• a second sampler configured to sample outputs of the second multi-input differential amplifier;
• a third sampler configured to sample outputs of the third multi-input differential amplifier;
• and
• a decoder configured to decode outputs of the first sample, the second sampler, and the third sampler to restore the input data,
• wherein the outputs of the differential amplifiers swing between VDD and (VDD−VSWING) and the outputs of the multi-input differential amplifiers have only VDD or (VDD−VSWING), and
• the VDD is a supply voltage supplied to the differential amplifiers.

A receiver which receives signals from a transmitter which maps 2-bit input data to one of codes in which a first voltage level of a first signal line, a second voltage level of a second signal line, and a third voltage level of a third signal line are set, and outputs the signals corresponding to the input data through the first signal line, the second signal line, and the third signal line which respectively have the first voltage level, the second voltage level, and the third voltage level corresponding to the mapped code, wherein even when the input data is changed, none of the first voltage level, the second voltage level, and the third voltage level is transitioned from ‘+1’ to ‘−1’ or from ‘−1’ to ‘+1’, and a number of signal line having a voltage level of ‘+1’ is the same as a number of signal line having a voltage level of ‘−1’, the receiver comprising:

• first comparators configured to compare a voltage of a first signal transmitted through the first signal line with reference voltages, respectively;
• second comparators configured to compare a voltage of a second signal transmitted through the second signal line with the reference voltages, respectively;
• third comparators configured to compare a voltage of a third signal transmitted through the third signal line with the reference voltages, respectively;
• and
• a decoder configured to decode outputs of the comparators to restore the input data,
• wherein each comparator outputs logic 1 when the voltage of the corresponding signal is greater than the corresponding reference voltage and outputs logic 0 when the voltage of the corresponding signal is smaller than the corresponding reference voltage,
• among the reference voltages, a first reference voltage has an intermediate value between the voltage level corresponding to ‘+1’ and the voltage level corresponding to ‘0’, and a second reference voltage has an intermediate value between the voltage level corresponding to ‘0’ and the voltage level corresponding to ‘−1’.

A data transmitting method used in a data transmitting/receiving system comprising:

• mapping 2-bit input data to one of codes, wherein a first voltage level of a first signal line, a second voltage level of a second signal line, and a third voltage level of a third signal line are set in each of the codes;
• and
• outputting signals corresponding to the input data through the first signal line, the second signal line, and the third signal line, which respectively have the first voltage level, the second voltage level, and the third voltage level corresponding to the mapped code,
• wherein each of the first voltage level, the second voltage level, and the third voltage level is ‘+1’, ‘0’ or ‘−1’, a number of signal line having a voltage level of ‘+1’ is the same as a number of signal line having a voltage level of ‘−1’,
• wherein IVDD0=0.5*(IVDD+1+IVDD−1) so that the current flowing through a power line is constant regardless of the input data, or IVSS0=0.5*(IVSS+1+IVSS−1) so that the current flowing through a ground line is constant regardless of the input data, and
• wherein IVDD+1 is the current flowing through the power line per voltage level of ‘+1’ IVDD−1 is the current flowing through the power line per voltage level of ‘−1’, IVDD0 is the current flowing through the power line per voltage level of ‘0’, IVSS−1 is the current flowing through the ground line per voltage level of ‘−1’, IVSS+1 is the current flowing through the ground line per voltage level of ‘+1’, and IVSS0 is the current flowing through the ground line per voltage level of ‘0’.