Variable gain amplifier

A variable gain amplifier, comprising:

• a first transistor group which is connected to an input terminal and an output terminal, and which forms a plurality of first differential pairs, the plurality of first differential pairs being connected in parallel and being configured to amplify a signal from the input terminal to output the amplified signal to the output terminal;
• a second transistor group which forms a plurality of second differential pairs connected in parallel to the input terminal, source-side terminals of respective transistors forming each of the plurality of second differential pairs being connected to the input terminal, and drain-side terminals of the respective transistors being connected to each other;
• a third transistor group which is connected in parallel to the output terminal, which forms a plurality of third differential pairs connected in cascade respectively to the plurality of second differential pairs formed by the second transistor group, a source-side terminal and a drain-side terminal of each transistor forming each third differential pair included in the plurality of third differential pairs being connected to the drain-side terminal of each transistor forming the second differential pair connected in cascade to the third differential pair and the output terminal, respectively;
• a controller configured to turn on/off the transistors in a unit of each of the first differential pair of the first transistor group, the second differential pair of the second transistor group, and the third differential pair of the third transistor group, so as to keep a total number of the number of transistors to be turned on in the first transistor group and the number of transistors to be turned on in the second transistor group at a constant value, and keep a total number of the number of transistors to be turned on in the first transistor group and the number of transistors to be turned on in the third transistor group at a constant value, to thereby control the first transistor group, the second transistor group, and the third transistor group;
• a first load element having one terminal connected to a ground and having another terminal connected to the input terminal;
• and
• a second load element having one terminal connected to a power supply line and having another terminal connected to the output terminal,
• wherein the plurality of first differential pairs formed by the first transistor group are connected in parallel between the other terminal of the first load element and the other terminal of the second load element,
• wherein the source-side terminal of each transistor of each of the plurality of second differential pairs formed by the second transistor group is connected to the other terminal of the first load element, and
• wherein the drain-side terminal of each transistor of each of the plurality of third differential pairs formed by the third transistor group is connected to the other terminal of the second load element.