Semiconductor device having stepped multi-stack transistor structure

A semiconductor device comprising:

• a substrate;
• a 1st transistor formed above the substrate, the 1st transistor comprising a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set;
• and
• a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor comprising a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set,
• wherein the 1st channel set has a greater width than the 2nd channel set,
• wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and
• wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

A semiconductor device comprising:

• a substrate;
• a 1st transistor formed above the substrate, the 1st transistor comprising at least two 1st channel layers and 1st and 2nd source/drain regions;
• and
• a 2nd transistor stacked above the 1st transistor in a vertical direction, the 2nd transistor comprising at least two 2nd channel layers and 3rd and 4th source/drain regions;
• wherein the 2nd source/drain region is partially overlapped by the 4th source/drain region in a vertical direction,
• wherein at least one of the two 1st channel layers is not vertically overlapped by any one of the 2nd channel layers, and
• wherein the semiconductor device further comprises a source/drain contact structure connected to the 2nd source/drain region through a space where the 4th source/drain region does not overlap the 2nd source/drain region in the vertical direction.