Controller to detect malfunctioning address of memory device
AssigneeRambus Inc.
InventorsAdrian E. Ong, Fan Ho
Life of this patent
Estimating the term…
Abstract
A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
Claims18
A method comprising:
- determining whether one or more address matching registers for storing a row address for repair are available in an external memory device;
- and
- based on a determination that the one or more address matching registers for storing the row address for repair are available in the external memory device:
- transmitting a first register setting command to initiate a row repair mode in the external memory device;
- transmitting an activation command comprising an indication of the row address for repair in the external memory device;
- transmitting a precharge command for precharging the row address for repair in the external memory device;
- and
- transmitting a second register setting command to terminate the row repair mode in the external memory device.
A controller comprising:
- an internal memory to store a row address for repair;
- and
- a first unit operatively coupled with the internal memory, the first unit to:
- determine whether one or more address matching registers for storing the row address for repair are available in an external memory device;
- and
- a second unit operatively coupled with the internal memory, the second unit to:
- based on a determination that the one or more address matching registers for storing the row address for repair are available in the external memory device:
- transmit a first register setting command to initiate a row repair mode in the external memory device;
- transmit an activation command comprising an indication of the row address for repair in the external memory device;
- transmit a precharge command for precharging the row address for repair in the external memory device;
- and
- transmit a second register setting command to terminate the row repair mode in the external memory device.
A DRAM comprising:
- one or more address matching registers for storing a row address for repair;
- and
- a register for storing an indication of whether the one or more address matching registers are available for storing a row address for repair;
- and
- circuitry to:
- receive a first register setting command to initiate a row repair mode in the DRAM;
- receive an activation command comprising an indication of the row address for repair in the DRAM;
- in response to receiving the activation command, repair the row address for repair in the DRAM;
- receive a precharge command for precharging the row address for repair in the DRAM;
- and
- receive a second register setting command to terminate the row repair mode in the DRAM.
Dependencies are inferred from the claim text.