Methods and apparatus for low jitter fractional output dividers

A system adapted to be coupled to an oscillator and operable to receive an oscillating signal from the oscillator, the system comprising:

• a first fractional output divider including a first input and a first output, the first input adapted to be coupled to an output of the oscillator and the first fractional output divider operable to generate a first output clock signal that has a first frequency equal to a fraction of the oscillating signal;
• a second fractional output divider including a second input, a second output, and a third output, the second input adapted to be coupled to the output of the oscillator and the second fractional output divider operable to generate a second output clock signal at the first frequency;
• an edge combining controller including a third input, a fourth input, and a fourth output, the third input coupled to the first output and the fourth input coupled to the second output, the edge combining controller operable to combine edges of the first output clock signal and the second output clock signal to generate an output clock signal having a second frequency different than the first frequency;
• and
• a multiplexer having a fifth input, a sixth input, a select input, and a fifth output, the fifth input coupled to the third output, the sixth input coupled to the fourth output, and the multiplexer operable to select between the fifth input and the sixth input for forwarding to the fifth output responsive to a logic signal received at the select input.

A method comprising:

• generating a delay parameter indicative of a phase difference between an output signal and an input clock signal edge;
• charging a capacitor for a first period of time with a first current that is proportional to the delay parameter to generate a first voltage on the capacitor that is proportional to the delay parameter;
• charging the capacitor for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage;
• comparing the voltage ramp to a reference voltage during the second period of time;
• asserting a rising edge on the output signal responsive to the voltage ramp equaling the reference voltage;
• and
• initiating a reset phase responsive to the rising edge on the output signal;
• and
• asserting a falling edge on the output signal at a fixed time from the rising edge responsive to the initiation of the reset phase.